• Journal of the Korean Ceramic Society
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• v.40 no.12
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• pp.1189-1196
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• 2003

Ferroelectric B $i_{3.25}$L $a_{0.75}$ $Ti_3$ $O_{12}$ (BLT) solution was synthesized by sol-gel process. BLT thin films were deposited on Pt/Ti $O_2$/ $SiO_2$/Si substrates by spin-coating. In this experiments, Bi(TMHD)$_3$, La(III)2-Methoxyethoxide, and Ti(IV) i-propoxide were used as starting materials, which were dissolved in 2-Methoxyethanol. Rapid Thermal Annealing (RTA) was used to promote crystallization of BLT thin films. The thin films with RTA process were compared with those with non-RTA process on electrical properties. After RTA process, the remanent polarization value (2Pr) of BLT thin films annealed at 72$0^{\circ}C$ was 20.46 $\mu$C/$\textrm{cm}^2$ which was approximately 27% higher than that of non-RTA process at 5 V.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.12
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• pp.1841-1851
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• 1990

Self-aligned gate GaAs MESFETs using ion beam deposited tungsten applicable to GaAs LSI fabrication process have been fabricated. Silicon implanted samples were annealed using isothermla two step RTA process and conventional one step RTA process. The electrical and physicla characteristics of annealed samples were investigated using Hall and I-V measurements. As results of measurements, activation characteristics of the isothermal two step RTA process are better than those of one step annealed ones. Using the developed processes, GaAs SAFETs (Self-Aligned Gate FET) have been fabricated and electdrical characteirstics are measured. As results, subthreshold currents of SAGFETs are 6x10**-10 A/\ulcorner, that is compatible to conventional MESFET, maximum transconductances of 0.75\ulcorner gate MESFET using one step RTA process and 2\ulcorner gate MESFET using isothermal two step RTA process are 18 mS/mm, 41 mS/mm respectively.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1424-1425
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• 2006

A four-step rapid thermal annealing (RTA) process is proposed in order to improve the throughput and stabilize the process, compared to the six-step RTA process. Effects of annealing on the properties of a structure mode of CMOS process in both cases were investigated. The implanted dopant(As, $BF_2$ and Ti/TiN) movement in silicon during different rapid thermal annealing conditions was studied using secondary ion mass spectroscopy (SIMS) technique. These results show that the four-step RTA process significantly improves time effect and throughput (15%) by the condition of ramping up compared to the six-step RTA process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.1
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• pp.11-16
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• 2016

The conduction behavior and electron concentration change in a-IGZO thin-films according to the RTA (rapid thermal annealing) were studied. The electrical characteristics of TFTs (thin-film-transistors) annealed by different temperatures were measured. The sheet resistance, electron concentration, and oxygen vacancy of a-IGZO film were measured by the four-point-probe-measurement, hall-effect-measurement, and XPS analysis. The RTA process increased the driving current of IGZO TFTs but the VTH shifted to the negative direction at the same time. When the RTA temperature is higher than $250^{\circ}C$, the leakage current at off-state increased significantly. This is attributed to the increase of oxygen vacancy resulting in the increase of electron concentration. We demonstrate that the RTA is a promising process to adjust the VTH of TFT because the RTA process can easily modify the electron concentration and control the conductivity of IGZO film with short process time.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.10 no.1
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• pp.42-47
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• 2000

The surface structure and the crystalline features in the near surface region have been investigated for CZ(Czochralski) grown Si wafers. Si wafers were annealed by RTA (Rapid Thermal Annealing) method in H$_2$ambient after mirror polished process. The densities of COPs (Crystal Originated Particles) after RTA process were remarkably decreased at the surface and in the region of 5um depth from the surface as well. terrace type surface structure which was formed by etching and re-arrangement of Si atoms during $H_2$annealing process also has been observed.

• Electrical & Electronic Materials
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• v.8 no.6
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• pp.737-743
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• 1995

Two step RTD(Rapid Thermal Diffussion) of P into silicon wafer using tungsten halogen lamp was used to fabricated very shallow n$^{+}$p junction. 1st RTD was performed in the temperature range of 800.deg. C for 60 see and the heating rate was in the 50.deg. C/sec. Phosphrous solid source was transfered on the silicon surface. 2nd RTD process was performed in the temperature range 1050.deg. C, 10sec. Using 2 step RTD we can obtain a shallow junction 0.13.mu.m in depth. After RTD, the Ti-silicide process was performed by the two step RTA(Rapid Thermal Annealing) to reduced the electric resistance and to improve the n$^{+}$p junction diode. The titanium thickness was 300.angs.. The condition of lst RTA process was 600.deg. C of 30sec and that of 2nd RTA process was varied in the range 700.deg. C, 750.deg. C, 800.deg. C for 10sec-60sec. After 2 step RTA, sheet resistance was 46.ohm../[]. Ti-silicide n+p junction diode was fabricated and I-V characteristics were measured.red.

• Journal of the Korean institute of surface engineering
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• v.28 no.2
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• pp.67-76
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• 1995

The microstructure of 95wt.%Pb/5wt.%Sn and 63wt.%Sn/37wt.%Pb solders for flip chip bonding process has been characterized. Solders were deposited by thermal evaporation and reflowed in the conventional furnace or by rapid thermal annealing(RTA) process. As-deposited films show columnar structure. The microstructure of furnace cooled 63Sn/37Pb solder shows typical lamellar form, but that of RTA treated solder has the structure showing an uniform dispersion of Pb-rich phase in Sn matrix. The grain size of 95Pb/5Sn solder reflowed in the furnace is about $5\mu\textrm{m}$, but the grain size of RTA treated solder is too small to be observed. The microstructure in 63Sn/37Pb solder bump shows the segregation of Pb phase in the Sn rich matrix regardless of reflowing method. The 63Sn/37Pb solder bump formed by RTA process shows more uniform microstructure. These result are related to the heat dissipation in the solder bump.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.8
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• pp.80-90
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• 1994

The ultra shallow junction was formed by 2-step RTP. Phosphorus solid source(P$_{2}O_{5}$) was transfered on wafer surface during RTG(Rapid Thermal Glass Transfer) of which process condition was 80$0^{\circ}C$ and 60sec. The process temperature and time of the RTD(Rapid Thermal Diffusion) were 950~105$0^{\circ}C$ during 5~15sec respectively sheet resistances were measured as 175~320$\Omega$/m and junction depth and dopth and dopant surface concentration were measured as 0.075~0.18$\mu$m and 5${\times}10^{19}cm^{4}$ respectively. Ti-silicide was formed by 2-step RTA after 300$\AA$ Titanium was deposited. The 1st RTA (2nd RTA) was carried out at the temperature of $600^{\circ}C$(700~80$0^{\circ}C$) for 30 seconds (10~60 seconds) under N$_2$ ambient. Sheet resistances after 2nd RTA were measured as 46~63$\Omega$/D. Si/Ti component ratio was evaulated as 1.6~1.9 from Auger depth profile. Ti-Silicided n-p junction diode (pattern size : 400$\times$400$\mu$m) was fabricated under the RTD(the process was carried out at the temperature of 100$0^{\circ}C$ for 10seconds) and 2nd RTA(theprocess was carried out at the temperature of 750$^{\circ}C$ for 60 seconds). Leakage current was measured 1.8${\times}10^{7}A/mm^{2}$ at 5V reverse voltage. Whent the RTD process condition is at the temperature of 100$0^{\circ}C$ for 10seconds and the 2nd RTA process condition is at the temperature of 75$0^{\circ}C$ for 60 seconds leakage current was 29.15${\times}10^{9}A$(at 5V).

• Proceedings of the Materials Research Society of Korea Conference
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• 2010.05a
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• pp.58.1-58.1
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• 2010

We have developed a novel crystallization process, where the crystallization temperature is lowered compared to the conventional RTA process and the metal contamination is lowered compared to the conventional VIC process. A very-thin a-Si film was deposited and crystallized at $550^{\circ}C$ for 3 h by the VIC process and then a thick a-Si film was deposited and crystallized by the RTA process at $680^{\circ}C$ for 5 min using the VIC poly-Si layer as a crystallization seed layer. The RTA crystallized temperature could be lowered up to $50^{\circ}C$, compared to RTA process alone. The poly-Si film appeared a needle-like growth front and relatively well-arranged (111) orientation. In addition, the Ni concentration in the poly-Si film was lowered to $3{\times}10^{17}\;cm^{-3}$ and that at the poly-Si/$SiO_2$ interface was lowered to $5{\times}10^{19}\;cm^{-3}$. The reduction in metal contamination could be greatly helpful to achieve a low leakage current in poly-Si TFT, which is the critical parameter for commercialization of AMOLED.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.379-382
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• 1988

In this paper optimal light source arraies are calculated to reduce slips in RTA process. A two-channel temperature controller is constructed on a board using IBM - XT to improve the temperature uniformity. The proposed RTA structure has also advantage of power dissipation.