• 한국세라믹학회지
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• 제40권12호
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• pp.1189-1196
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• 2003

Sol-gel법으로 강유전성 B $i_{3.25}$L $a_{0.75}$ $Ti_3$ $O_{12}$ (BLT) stock solution을 합성하고 Pt/Ti $O_2$/ $SiO_2$/Si 기판위에 스핀코팅법으로 BLT 박막을 증착하였다. 본 실험에서는 Bi(TMHD)$_3$, La(III)2-Methoxyethoxide, Ti(IV)i-propoxide를 출발물질로 사용하였으며 2-Methoxyethanol을 용매로 사용하였다. 급속열처리(RTA)가 BLT 박막의 결정성장을 촉진시키기 위해 사용되었고, RTA를 실시한 시편과 RTA를 실시하지 않은 시편의 전기적 특성을 비교하였다. RTA를 실시한 후 72$0^{\circ}C$에서 로 열처리 한 BLT 박막의 경우 5V 인가 전압 하에서 2Pr 값은 RTA를 실시하지 않은 경우보다 27% 증가한 20.46$\mu$C/$ extrm{cm}^2$이었다.

• 대한전자공학회논문지
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• 제27권12호
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• pp.1841-1851
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• 1990

Self-aligned gate GaAs MESFETs using ion beam deposited tungsten applicable to GaAs LSI fabrication process have been fabricated. Silicon implanted samples were annealed using isothermla two step RTA process and conventional one step RTA process. The electrical and physicla characteristics of annealed samples were investigated using Hall and I-V measurements. As results of measurements, activation characteristics of the isothermal two step RTA process are better than those of one step annealed ones. Using the developed processes, GaAs SAFETs (Self-Aligned Gate FET) have been fabricated and electdrical characteirstics are measured. As results, subthreshold currents of SAGFETs are 6x10**-10 A/\ulcorner, that is compatible to conventional MESFET, maximum transconductances of 0.75\ulcorner gate MESFET using one step RTA process and 2\ulcorner gate MESFET using isothermal two step RTA process are 18 mS/mm, 41 mS/mm respectively.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
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• pp.1424-1425
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• 2006

A four-step rapid thermal annealing (RTA) process is proposed in order to improve the throughput and stabilize the process, compared to the six-step RTA process. Effects of annealing on the properties of a structure mode of CMOS process in both cases were investigated. The implanted dopant(As, $BF_2$ and Ti/TiN) movement in silicon during different rapid thermal annealing conditions was studied using secondary ion mass spectroscopy (SIMS) technique. These results show that the four-step RTA process significantly improves time effect and throughput (15%) by the condition of ramping up compared to the six-step RTA process.

• 한국전기전자재료학회논문지
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• 제29권1호
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• pp.11-16
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• 2016

The conduction behavior and electron concentration change in a-IGZO thin-films according to the RTA (rapid thermal annealing) were studied. The electrical characteristics of TFTs (thin-film-transistors) annealed by different temperatures were measured. The sheet resistance, electron concentration, and oxygen vacancy of a-IGZO film were measured by the four-point-probe-measurement, hall-effect-measurement, and XPS analysis. The RTA process increased the driving current of IGZO TFTs but the VTH shifted to the negative direction at the same time. When the RTA temperature is higher than $250^{\circ}C$, the leakage current at off-state increased significantly. This is attributed to the increase of oxygen vacancy resulting in the increase of electron concentration. We demonstrate that the RTA is a promising process to adjust the VTH of TFT because the RTA process can easily modify the electron concentration and control the conductivity of IGZO film with short process time.

• 한국결정성장학회지
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• 제10권1호
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• pp.42-47
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• 2000

일반적인 쵸크랄스키(CZ)방법으로 성장된 실리콘 단결정봉(Ingot)을 가공하여 경면 연마한 후 RTA법으로 수소 분위기에서 열처리하여 실리콘 웨이퍼 표면 및 표면 근처의 특성 변화에 대하여 고찰하였다 수소 열처리를 통하여 표면의 COP (결정결함)가 현저히 감소하는 것을 확인하였고 깊이 5um까지의 영역에서도 결정결함의 밀도가 감소하였다. 또한 수소 열처리에 의해 실리콘 웨이퍼 표면이 에칭 및 실리콘의 재배열에 의해 형성되는 테라스(Terrace) 형태도 관찰되었다.

• E2M - 전기 전자와 첨단 소재
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• 제8권6호
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• pp.737-743
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• 1995

Two step RTD(Rapid Thermal Diffussion) of P into silicon wafer using tungsten halogen lamp was used to fabricated very shallow n$^{+}$p junction. 1st RTD was performed in the temperature range of 800.deg. C for 60 see and the heating rate was in the 50.deg. C/sec. Phosphrous solid source was transfered on the silicon surface. 2nd RTD process was performed in the temperature range 1050.deg. C, 10sec. Using 2 step RTD we can obtain a shallow junction 0.13.mu.m in depth. After RTD, the Ti-silicide process was performed by the two step RTA(Rapid Thermal Annealing) to reduced the electric resistance and to improve the n$^{+}$p junction diode. The titanium thickness was 300.angs.. The condition of lst RTA process was 600.deg. C of 30sec and that of 2nd RTA process was varied in the range 700.deg. C, 750.deg. C, 800.deg. C for 10sec-60sec. After 2 step RTA, sheet resistance was 46.ohm../[]. Ti-silicide n+p junction diode was fabricated and I-V characteristics were measured.red.

• 한국표면공학회지
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• 제28권2호
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• pp.67-76
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• 1995

The microstructure of 95wt.%Pb/5wt.%Sn and 63wt.%Sn/37wt.%Pb solders for flip chip bonding process has been characterized. Solders were deposited by thermal evaporation and reflowed in the conventional furnace or by rapid thermal annealing(RTA) process. As-deposited films show columnar structure. The microstructure of furnace cooled 63Sn/37Pb solder shows typical lamellar form, but that of RTA treated solder has the structure showing an uniform dispersion of Pb-rich phase in Sn matrix. The grain size of 95Pb/5Sn solder reflowed in the furnace is about $5\mu\textrm{m}$, but the grain size of RTA treated solder is too small to be observed. The microstructure in 63Sn/37Pb solder bump shows the segregation of Pb phase in the Sn rich matrix regardless of reflowing method. The 63Sn/37Pb solder bump formed by RTA process shows more uniform microstructure. These result are related to the heat dissipation in the solder bump.

• 전자공학회논문지A
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• 제31A권8호
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• pp.80-90
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• 1994

The ultra shallow junction was formed by 2-step RTP. Phosphorus solid source(P$_{2}O_{5}$) was transfered on wafer surface during RTG(Rapid Thermal Glass Transfer) of which process condition was 80$0^{\circ}C$ and 60sec. The process temperature and time of the RTD(Rapid Thermal Diffusion) were 950~105$0^{\circ}C$ during 5~15sec respectively sheet resistances were measured as 175~320$\Omega$/m and junction depth and dopth and dopant surface concentration were measured as 0.075~0.18$\mu$m and 5${\times}10^{19}cm^{4}$ respectively. Ti-silicide was formed by 2-step RTA after 300$\AA$ Titanium was deposited. The 1st RTA (2nd RTA) was carried out at the temperature of $600^{\circ}C$(700~80$0^{\circ}C$) for 30 seconds (10~60 seconds) under N$_2$ ambient. Sheet resistances after 2nd RTA were measured as 46~63$\Omega$/D. Si/Ti component ratio was evaulated as 1.6~1.9 from Auger depth profile. Ti-Silicided n-p junction diode (pattern size : 400$\times$400$\mu$m) was fabricated under the RTD(the process was carried out at the temperature of 100$0^{\circ}C$ for 10seconds) and 2nd RTA(theprocess was carried out at the temperature of 750$^{\circ}C$ for 60 seconds). Leakage current was measured 1.8${\times}10^{7}A/mm^{2}$ at 5V reverse voltage. Whent the RTD process condition is at the temperature of 100$0^{\circ}C$ for 10seconds and the 2nd RTA process condition is at the temperature of 75$0^{\circ}C$ for 60 seconds leakage current was 29.15${\times}10^{9}A$(at 5V).

• 한국재료학회:학술대회논문집
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• 한국재료학회 2010년도 춘계학술발표대회
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• pp.58.1-58.1
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• 2010

We have developed a novel crystallization process, where the crystallization temperature is lowered compared to the conventional RTA process and the metal contamination is lowered compared to the conventional VIC process. A very-thin a-Si film was deposited and crystallized at $550^{\circ}C$ for 3 h by the VIC process and then a thick a-Si film was deposited and crystallized by the RTA process at $680^{\circ}C$ for 5 min using the VIC poly-Si layer as a crystallization seed layer. The RTA crystallized temperature could be lowered up to $50^{\circ}C$, compared to RTA process alone. The poly-Si film appeared a needle-like growth front and relatively well-arranged (111) orientation. In addition, the Ni concentration in the poly-Si film was lowered to $3{\times}10^{17}\;cm^{-3}$ and that at the poly-Si/$SiO_2$ interface was lowered to $5{\times}10^{19}\;cm^{-3}$. The reduction in metal contamination could be greatly helpful to achieve a low leakage current in poly-Si TFT, which is the critical parameter for commercialization of AMOLED.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.379-382
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• 1988

In this paper optimal light source arraies are calculated to reduce slips in RTA process. A two-channel temperature controller is constructed on a board using IBM - XT to improve the temperature uniformity. The proposed RTA structure has also advantage of power dissipation.