• Journal of the Korean Graphic Arts Communication Society
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• v.14 no.1
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• pp.17-29
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• 1996

N-substituted acrylamide hydrogel is reported to have the feature of bing transparent and sensitive enough to response to a temperature stimulus below the temperature of phase transition. Especially at the near of 35 C it becomes shrunk and opaque very quickly. It has also the characteristic of reversing swelling and shrinking. The experiment showed that it is possible to produce a functional gel of super water absorption with the process of free radical polymerizing PVA(polyvinylalcohol) and PAA(polyacrylamide), and crosslinking. The ratio of shrinking and swelling caused by copolymerization rises 10% to 80% at the each temperature of 20 C, 30 C, 40 C, respectively. Phase transition temperature of this gel by copolymerization is50 C while that of ordinary N-substituted acrylamides is between 32~35 C. This temperature reaches the rearing limit of animals and plants so that volumetric transition polymer gel can be ulilized in varying fields such as agriculture/gardening which are water-using field, on-off switch sensing temperature and volumetric variation, processing of liquid wastes and civil engineering works, architecture and electronics. We have no doubt that this material will be the high-functional resin in the hi-tech age of the near future.

• Journal of Advanced Information Technology and Convergence
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• v.8 no.2
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• pp.59-67
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• 2018

The minimum power supply voltage of a typical bandgap current reference (BGCR) is limited by operating temperature and input common mode range (ICMR) of a feedback amplifier. A new BGCR using a bandgap voltage generator (BGVG) is proposed to minimize the effect of temperature, supply voltage, and process variation. The BGVG is designed with proportional to absolute temperature (PTAT) characteristic, and a feedback amplifier is designed with weak-inversion transistors for low voltage operation. It is verified with a $0.18-{\mu}m$ CMOS process with five corners for MOS transistors and three corners for BJTs. The proposed circuit is superior to other reported current references under temperature variation from $-40^{\circ}C$ to $120^{\circ}C$ and power supply variation from 1.2 V to 1.8 V. The total power consumption is $126{\mu}W$ under the conditions that the power supply voltage is 1.2 V, the output current is $10{\mu}A$, and the operating temperature is $20^{\circ}C$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.94-99
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• 2010

This paper presents a charge pump architecture for correcting the current mismatch due to the PVT variation. In general, the current mismatch of the charge pump should be minimized to improve the phase noise and spur performance of the PLL. In order to correct the current mismatch of the charge pump, the current difference is detected by the replica charge pump and fed back into the main charge pump. This scheme is very simple and guarantees the high accuracy compared with the prior works. Also, it shows a good dynamic performance because the mismatch is corrected continuously. It is implemented in 0.13um CMOS process and the die area is $100{\mu}m\;{\times}\;160{\mu}m$. The voltage swing is from 0.2V to 1V at supply voltage of 1.2V. The charging and discharging currents are $100{\mu}A$, respectively and the current mismatch due to the PVT variation is less than 1%.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.653-654
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• 2006

A Pre-emphasis transmitter for DRAM bus system has achieved 3.2Gbps/pin operation at 1.8V supply voltage with 0.18um CMOS process. The transmitter has 800MHz PLL to generate 4 phase clocks. The 4 phase clocks are used for input clock of PRBS and multiplexing. One tap pre-emphasis is used to reduce inter symbol interference (ISI) caused by channel low pass effects. The analog calibration makes the optimized driver impedance independent with the PVT variation.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.59-65
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• 2013

Conventional synchronous design circuits cannot only satisfy the timing requirement of the low voltage digital systems, but also they may generate wrong outputs under the influence of PVT variations and aging effects. Therefore, in this paper, a NCL (Null Convention Logic) design as an asynchronous design method has been proposed, where the NCL method doesn't require any timing analysis, and it has a very simple design methodology. Base on the NCL method, a new low power reliable ALU has been designed and implemented using MagnaChip-SKhynix 0.18um CMOS technology. The experimental results of the proposed NCL ALU have been compared to those of a conventional pipelined ALU in terms of power consumption and speed.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.28 no.4
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• pp.152-158
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• 2018

PVT (Physical Vapor Transport) method has advantages in producing high quality, large scale wafers where many researches are being carried out to commercialize nitride semiconductors. However, complex process variables cause various defects when it had non-equilibrium growth conditions. Annealing process after crystal growth has been widely used to enhance the crystallinity. It is important to set appropriate temperature, pressure, and annealing time to improve crystallinity effectively. In this study, the effect of the annealing conditions on the crystalline structure variation of the AlN single crystal grown by PVT method was investigated with synchrotron whitebeam X-ray topography, electron backscattered diffraction (EBSD), and Rietveld refinement. X-ray topography analysis showed secondary phases, sub-grains, impurities including carbon inclusion in the single crystal before annealing. EBSD analyses identified that sub-grains with slightly tilted basal plane appeared and the overall number of grains increased after the annealing process. Rietveld refinement showed that the stress caused by the temperature gradient during the annealing process between top and bottom in the hot zone not only causes distortion of grains but also changes the lattice constant.

• Journal of the Korean Ceramic Society
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• v.48 no.4
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• pp.312-315
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• 2011

The effect of slurry composition and wafer flatness on a material removal rate (MRR) and resulting surface roughness which are evaluation parameters to determine the CMP characteristics of the on-axis 6H-SiC substrate were systematically investigated. 2-inch SiC wafers were fabricated from the ingot grown by a conventional physical vapor transport (PVT) method were used for this study. The SiC substrate after the CMP process using slurry added oxidizers into slurry consisted of KOH-based colloidal silica and nano-size diamond particle exhibited the significant MRR value and a fine surface without any surface damages. SiC wafers with high bow value after the CMP process exhibited large variation in surface roughness value compared to wafer with low bow value. The CMPprocessed SiC wafer having a low bow value of 1im was observed to result in the Root-mean-square height (RMS) value of 2.747 A and the mean height (Ra) value of 2.147 A.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.1
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• pp.61-67
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• 2014

Conventional synchronous circuits in low power required systems such as sensor systems cannot only satisfy the timing requirement of the low voltage digital systems, but also they may generate wrong outputs under the influence of PVT variations and aging effects. Therefore, in the reliable ultra-low power design, asynchronous circuits have recently been reconsidered as a solution for scaling issues. However, it is not easy to totally replace synchronous circuits with asynchronous circuits in the digital systems, so the interfacing between the synchronous and asynchronous circuits is indispensable for the digital systems. This paper presents a new design for interfacing between asynchronous circuits and synchronous circuits, and the interface circuits are applied to a $4{\times}4$ multiplier logic designed using 0.11um technology.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.2
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• pp.112-118
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• 2015

Conventional synchronous circuits cannot keep the circuit performance, and cannot even guarantee correct operations under the influence of PVT variations and aging effects in the nanometer regime. Therefore, in this paper, a DI (delay insensitive) design based NCL (Null Convention Logic) design methodology with a very simple design structure has been used to design digital systems, which is one of well-known asynchronous design methods robust to various variations and does not require any timing analysis. Because circuit-level structures of conventional NCL gates have weakness of low speed, high area overhead or high wire complexity, this paper proposes a new lNCL gates designed at the transistor level for high-speed, low area overhead, and low wire complexity. The proposed NCL gate libraries have been compared to the conventional NCL gates in terms of circuit delay, area and power consumption using a asynchronous multiplier implemented in dongbu 0.11um CMOS technology.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.1
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• pp.120-131
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• 2016

In this paper, a 512b MTP memory IP is designed by using MTP memory cells which are written by the FN (Fowler-Nordheim) tunneling method with only MV (medium voltage) devices of 5V which uses the back-gate bias, that is VNN (negative voltage). The used MTP cell consists of a CG (control gate) capacitor, a TG (tunnel gate) transistor, and a select transistor. To reduce the size of the MTP memory cell, just two PWs (P-wells) are used: one for the TG and the select transistors; and the other for the CG capacitor. In addition, just one DNW (deep N-well) is used for the entire 512b memory cell array. VPP and VNN generators supplying pumping voltages of ${\pm}8V$ which are insensitive to PVT variations since VPP and VNN level detectors are designed by a regulated voltage, V1V (=1V), provided by a BGR voltage generator.