1 |
Scott Hauck, "Asynchronous Design Methodologies: An Overview", Proceeding of the IEEE, Vol. 86, No. 1, pp. 69-93, Jan. 1995.
|
2 |
H.Van Gageldonk et al., "An Asynchronous Low-power 80c51 Microcon- troller," Proc. International Symposium Advanced Research in Asynchronous Circuits and Systems, pp. 96-107, 1998.
|
3 |
Kyung Ki Kim, "Minimal Leakage Pattern Generator," 한국산업정보학회논문지, V. 16, No. 5, pp.1-8, 2011년 12월.
과학기술학회마을
|
4 |
Scott C. Smith, Jia Di, "Designing Asynchronous Circuits using NULL Convention Logic (NCL)," Morgan&Calypool Publishers, 2009.
|
5 |
M. Singh and S. M. Nowick, "Teaching Asynchronous Design in Digital Integrated Circuits," IEEE Trans. on Education, Vol. 47, No. 3, pp. 397-404, Aug. 2004.
DOI
ScienceOn
|
6 |
Kyung Ki Kim, "나노 MOSFET 공정에서의 초저전압 NCL 회로 설계," 한국산업정보학회논문지, V. 17, No. 4, pp.17-23, 2012년 08월.
과학기술학회마을
DOI
ScienceOn
|
7 |
R. D. Jorgenson, M. S. Hagedorn, T. H. Friddell, "Ultralow-Power Operation in Subthreshold Regimes Applying Clockless Logic," Proceedings of The IEEE, Vol. 98, No. 2, pp. 299-314, Feb. 2010.
DOI
ScienceOn
|
8 |
C. M. Smith, S. C. Smith, " Comparison of NULL Convention Booth2 Multipliers," IEEE MWSCAS, pp. 394-397, 2012.
|
9 |
F. A. Parsan, S. C. Smith, "CMOS implementation of static threshold gates with hysteresis: A new approach," IEEE VLSI-SoC, pp. 41-45, 2012.
|
10 |
F. A. Parsan, S. C. Smith, "CMOS implementation Comparison of NCL Gates," IEEE MWSCAS, pp. 394-397, 2012.
|