• Title/Summary/Keyword: Nano-Electronics

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Fabrication of Multi-Fin-Gate GaN HEMTs Using Honeycomb Shaped Nano-Channel (벌집구조의 나노채널을 이용한 다중 Fin-Gate GaN 기반 HEMTs의 제조 공정)

  • Kim, Jeong Jin;Lim, Jong Won;Kang, Dong Min;Bae, Sung Bum;Cha, Ho Young;Yang, Jeon Wook;Lee, Hyeong Seok
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.33 no.1
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    • pp.16-20
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    • 2020
  • In this study, a patterning method using self-aligned nanostructures was introduced to fabricate GaN-based fin-gate HEMTs with normally-off operation, as opposed to high-cost, low-productivity e-beam lithography. The honeycomb-shaped fin-gate channel width is approximately 40~50 nm, which is manufactured with a fine width using a proposed method to obtain sufficient fringing field effect. As a result, the threshold voltage of the fabricated device is 0.6 V, and the maximum normalized drain current and transconductance of Gm are 136.4 mA/mm and 99.4 mS/mm, respectively. The fabricated devices exhibit a smaller sub-threshold swing and higher Gm peak compared to conventional planar devices, due to the fin structure of the honeycomb channel.

Well-Aligned Nano-Sized Pores Using Aluminum Thin Film Fabricated by Aluminum Anodized Oxidation Method (알루미늄 박막을 이용하여 양극산화법으로 제작한 규칙적으로 정렬된 미세기공)

  • Han, Ga-Ram;Yun, Tae-Uk;Kang, Min-Ki;NamGung, Hyun-Min;Kim, Chang-Kyo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2010.06a
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    • pp.207-207
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    • 2010
  • 알루미늄 양극산화 기술은 저가로 공정이 가능하고, 경제적이며 규칙적인 배열의 나노 미터 크기의 미세기공을 형성할 수 있다는 장점을 가지고 있다. 인가전압, 양극산화 용액의 종류, 용액의 농도 및 온도 등의 양극산화 조건을 변화시킴에 따라 나노 기공의 직경 및 길이, 밀도 조절이 용이하다. 알루미늄 판 (aluminum plate)을 이용한 양극산화 기술은 상대적으로 많이 알려져 있으나 알루미늄 박막을 이용한 양극산화기술은 아직도 확립되어 있지 않다. 본 실험에서는 실리콘 기판에 Al을 $5000{\AA}$$8000{\AA}$으로 증착시켜서 기판으로 이용하였다. 아주 얇은 두께의 Al은 작은 변화에도 민감하게 반응하기 때문에 공정 변수인 온도와 전압의 정밀한 제어가 되어야 나노 기공의 크기 조절이 가능한 것을 확인하였다.

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CMOS-Memristor Hybrid 4-bit Multiplier Circuit for Energy-Efficient Computing

  • Vo, Huan Minh;Truong, Son Ngoc;Shin, Sanghak;Min, Kyeong-Sik
    • Journal of IKEEE
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    • v.18 no.2
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    • pp.228-233
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    • 2014
  • In this paper, we propose a CMOS-memristor hybrid circuit that can perform 4-bit multiplication for future energy-efficient computing in nano-scale digital systems. The proposed CMOS-memristor hybrid circuit is based on the parallel architecture with AND and OR planes. This parallel architecture can be very useful in improving the power-delay product of the proposed circuit compared to the conventional CMOS array multiplier. Particularly, from the SPECTRE simulation of the proposed hybrid circuit with 0.13-mm CMOS devices and memristors, this proposed multiplier is estimated to have better power-delay product by 48% compared to the conventional CMOS array multiplier. In addition to this improvement in energy efficiency, this 4-bit multiplier circuit can occupy smaller area than the conventional array multiplier, because each cross-point memristor can be made only as small as $4F^2$.

Characteristic Analysis of LDO Regulator According to Process Variation (공정변화에 따른 LDO 레귤레이터의 특성 분석)

  • Park, Won-Kyeong;Kim, Ji-Man;Heo, Yun-Seok;Park, Yong-Su;Song, Han-Jung
    • 전자공학회논문지 IE
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    • v.48 no.4
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    • pp.13-18
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    • 2011
  • In this paper, we have examined electrical characteristics of LDO regulator according to the process variation using a 1 ${\mu}m$ 20 V high voltage CMOS process. The electrical analysis of LDO regulator have been performed with three kind of SPICE parameter sets (Typ : typical, FF : fast, SS : slow) by process variation which cause change of SPICE parameter such as threshold voltage and effective channel length of MOS devices. From simulation results, we confirmed that in case of SS type SPICE parameter set, the LDO regulator has 3.6 mV/V line regulation, 0.4 mV/mA load regulation and 0.86 ${\mu}s$ output voltage settling time. And in case of Typ type SPICE parameter set, the LDO regulatorhas 4.2 mV/V line regulation, 0.44 mV/mA load regulation and 0.62 ${\mu}s$ output voltage settling time. Finally, in the FF type SPICE parameter set, the LDO regulator has 7.0 mV/V line regulation, 0.56 mV/mA load regulation and 0.27 ${\mu}s$ output voltage settling time.

The Study of Ni-Pd Alloy Characteristics to Form a NiSi for Shallow S/D Junction (Shallow S/D Junction에 적용 가능한 NiSi를 형성하기 위한 Ni-Pd 합금의 특성 연구)

  • Lee, Won-Jae;Oh, Soon-Young;Agchbayar, Tuya;Yun, Jang-Gn;Kim, Yong-Jin;Zhang, Ying-Ying;Zhong, Zhun;Kim, Do-Woo;Cha, Han-Seob;Heo, Sang-Bum;Wang, Jin-Suk;Lee, Hi-Deok
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.603-606
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    • 2005
  • In this paper, the formation and thermal stability of Ni-silicide using Ni-Pd alloys is studied for ultra shallow S/D junction of nano-scale CMOSFETs. There are no different effects when Ni-Pd is used in single structure and TiN capping structure. But, in case of Cobalt interlayer structure, it was found that Pure Ni had lower sheet resistance than Ni-Pd, because of a thick silicide. Also, Ni-Pd has merits that surface of silicide and interface between silicide and silicon have a good morphology characteristics. As a result, Ni-Pd is an optimal candidate for shallow S/D junction when cobalt is used for thermal stability.

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Dependence of Analog and Digital Performance on Carrier Direction in Strained-Si PMOSFET (Strained-Si PMOSFET에서 디지털 및 아날로그 성능의 캐리어 방향성에 대한 의존성)

  • Han, In-Shik;Bok, Jung-Deuk;Kwon, Hyuk-Min;Park, Sang-Uk;Jung, Yi-Jung;Shin, Hong-Sik;Yang, Seung-Dong;Lee, Ga-Won;Lee, Hi-Deok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.8
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    • pp.23-28
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    • 2010
  • In this paper, comparative analysis of digital and analog performances of strained-silicon PMOSFETs with different carrier direction were performed. ID.SAT vs. ID.OFF and output resistance, Rout performances of devices with <100> carrier direction were better than those of <110> direction due to the greater carrier mobility of <100> channel direction. However, on the contrary, NBTI reliability and device matching characteristics of device with <100> carrier direction were worse than those with <110> carrier direction. Therefore, simultaneous consideration of analog and reliability characteristics as well as DC device performance is highly necessary when developing mobility enhancement technology using the different carrier direction for nano-scale CMOSFETs.

Recent Advances in Eco-friendly Nano-ink Technology for Display and Semiconductor Application (디스플레이 반도체 기술 적용을 위한 청정 나노잉크 제조 기술)

  • Kim, Jong-Woong;Hong, Sung-Jei;Kim, Young-Seok;Kim, Young-Sung;Lee, Jeong-No;Kang, Nam-Kee
    • Journal of the Microelectronics and Packaging Society
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    • v.17 no.1
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    • pp.33-39
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    • 2010
  • Printing technologies have been indicated as alternative methods for patterning conductive, semi-conductive or insulative materials on account of their low-cost, large-area patternability and pattern flexibility. For application of the printing technologies in manufacture of semiconductor or display modules, ink or paste composed of nanoparticles, solvent and additives are basically needed. Here, we report recent advances in eco-friendly nano-ink technology for semiconductor and display technology. Then, we will introduce an eco-friendly ink formation technology developed in our group with an example of manufacturing $SiO_2$ nanopowders and inks. We tried to manufacture ultrafine $SiO_2$ nanoparticles by applying a low-temperature synthetic method, and then attempted to fabricate the printed $SiO_2$ film onto the glass substrate to see whether the $SiO_2$ nanoparticles are feasible for the printing or not. Finally, the electrical characteristics of the films were measured to investigate the effect of the manufacturing parameters.

A Study of the Temperature Dependency for Photocatalytic VOC Degradation Chamber Test Under UVLED Irradiations (UVLED 광원을 이용한 광촉매 VOC 제거 특성 평가시 온도에 따른 농도 변화에 관한 연구)

  • Moon, Jiyeon;Lee, Kyusang;Kim, Seonmin
    • Korean Chemical Engineering Research
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    • v.53 no.6
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    • pp.755-761
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    • 2015
  • Photocatalytic VOCs removal test in gas phase is generally performed by placing the light source on the outside due to maintaining a constant temperature inside the test chamber. The distance between light source and photocatalysts is importantin the VOC degradation test since the intensity of light is rapidly decreased as the distance farther. Especially, for the choice of light source as UVLED, this issue is more critical because UVLED light source emits lots of heat and it is hard to measure the exact concentration of VOCs due to changed temperature in the test chamber. In this study, we modified VOC removal test chamber base on the protocol of air cleaner test and evaluated the efficiency of photocatalystunder UVLED irradiation. Photocatalystsof two different samples (commercial $TiO_2$ and the synthesized vanadium doped $TiO_2$) weretested for the p-xylene degradation in the closed chamber system and compared with each other in order to exclude any experimental uncertainties. During the VOC removal test, VOC concentrations were monitored and corrected at regular time intervals because the temperature in the chamber increases ${\sim}20^{\circ}C$ due tothe heat of UVLED. The results showed that theconversion ratio of p-xylene has 40~43% difference before and after the temperature correction. Based on those results, we conclude that the VOC concentration correction must be required for the VOC removal test in a closed chamber system under UVLED light source and obtained the corrected efficiencies of various photocatlysts.

Wavelength Interrogation Technique for Bragg Reflecting Strain Sensors Based on Arrayed Waveguide Grating (도파로 어레이 격자를 이용한 광섬유 브래그 스트레인 센서의 반사파장 신호 복원 기술)

  • Seo, Jun-Kyu;Kim, Kyung-Jo;Oh, Min-Cheol;Lee, Sang-Min;Kim, Young-Jae;Kim, Myung-Hyun
    • Korean Journal of Optics and Photonics
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    • v.19 no.1
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    • pp.68-72
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    • 2008
  • Fiber-optic strain sensors based on Bragg reflection gratings produce the change of reflection spectrum when an external stress is applied on the sensor. To measure the Bragg reflection wavelength in high speed, an arrayed waveguide grating device is incorporated in this work. By monitoring the output power from each channel of the AWG, the peak wavelength corresponding to the applied strain could be obtained. To enhance the accuracy of the AWG wavelength interrogation system, a chirped fiber Bragg grating with a 3-dB bandwith of 5.4 nm is utilized. The high-speed response of the proposed system is demonstrated by measuring a fast varying strain produced by the damped oscillation of a cantilever. An oscillation frequency of 17.8 Hz and a damping time constant of 0.96 second are obtained in this measurement.

Reduction of Barrier Height between Ni-silicide and p+ source/drain for High Performance PMOSFET (고성능 PMOSFET을 위한 Ni-silicide와 p+ source/drain 사이의 barrier height 감소)

  • Kong, Sun-Kyu;Zhang, Ying-Ying;Park, Kee-Young;Li, Shi-Guang;Zhong, Zhun;Jung, Soon-Yen;Yim, Kyoung-Yean;Lee, Ga-Won;Wang, Jin-Suk;Lee, Hi-Deok
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.11a
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    • pp.157-157
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    • 2008
  • As the minimum feature size of semiconductor devices scales down to nano-scale regime, ultra shallow junction is highly necessary to suppress short channel effect. At the same time, Ni-silicide has attracted a lot of attention because silicide can improve device performance by reducing the parasitic resistance of source/drain region. Recently, further improvement of device performance by reducing silicide to source/drain region or tuning the work function of silicide closer to the band edge has been studied extensively. Rare earth elements, such as Er and Yb, and Pd or Pt elements are interesting for n-type and p-type devices, respectively, because work function of those materials is closer to the conduction and valance band, respectively. In this paper, we increased the work function between Ni-silicide and source/drain by using Pd stacked structure (Pd/Ni/TiN) for high performance PMOSFET. We demonstrated that it is possible to control the barrier height of Ni-silicide by adjusting the thickness of Pd layer. Therefore, the Ni-silicide using the Pd stacked structure could be applied for high performance PMOSFET.

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