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Characteristic Analysis of LDO Regulator According to Process Variation  

Park, Won-Kyeong (Department of Nano Engineering, Inje University)
Kim, Ji-Man (Department of Nano System Engineering, Inje University)
Heo, Yun-Seok (Department of Nano System Engineering, Inje University)
Park, Yong-Su (Department of Electronics, Chung Cheong University)
Song, Han-Jung (Department of Nano Engineering, Inje University)
Publication Information
전자공학회논문지 IE / v.48, no.4, 2011 , pp. 13-18 More about this Journal
Abstract
In this paper, we have examined electrical characteristics of LDO regulator according to the process variation using a 1 ${\mu}m$ 20 V high voltage CMOS process. The electrical analysis of LDO regulator have been performed with three kind of SPICE parameter sets (Typ : typical, FF : fast, SS : slow) by process variation which cause change of SPICE parameter such as threshold voltage and effective channel length of MOS devices. From simulation results, we confirmed that in case of SS type SPICE parameter set, the LDO regulator has 3.6 mV/V line regulation, 0.4 mV/mA load regulation and 0.86 ${\mu}s$ output voltage settling time. And in case of Typ type SPICE parameter set, the LDO regulatorhas 4.2 mV/V line regulation, 0.44 mV/mA load regulation and 0.62 ${\mu}s$ output voltage settling time. Finally, in the FF type SPICE parameter set, the LDO regulator has 7.0 mV/V line regulation, 0.56 mV/mA load regulation and 0.27 ${\mu}s$ output voltage settling time.
Keywords
LDO regulator; SPICE parameters; Semiconductor process; Simulation;
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