• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.4 s.346
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• pp.23-30
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• 2006

This paper describes the short-channel effect(SCE), corner effect of nano-scale MuGFETs(Multiple-Gate FETs) by three-dimensional simulation. We can extract the equivalent gate number of MuGFETs(Double-gate=2, Tri-gate=3, Pi-gate=3.14, Omega-gate=3.4, GAA=4) by threshold voltage model. Using the extracted gate number(n) we can calculate the natural length for each gate devices. We established a scaling theory for MuGFETs, which gives a optimization to avoid short channel effects for the device structure(silicon thickness, gate oxide thickness). It is observed that the comer effects decrease with the reduction of doping concentration and gate oxide thickness when the radius of curvature is larger than 17 % of the channel width.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.1
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• pp.135-141
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• 2014

In this paper, the device design guideline to reduce the threshold voltage variation with fin width in junctionless MuGFET has been suggested. It has been observed that the threshold voltage variation was increased with increase of fin width in junctionless MuGFETs. To reduce the threshold voltage variation with fin width in junctionless MuGFETs, 3-dimensional device simulation with different gate dielectric materials, silicon film thickness, and an optimized fin number has been performed. The simulation results showed that the threshold voltage variation can be reduced by the gate dielectric materials with a high dielectric constant such as $La_2O_3$ and the silicon film with ultra-thin thickness even though the fin width is increased. Particularly, the reduction of the threshold voltage variation and the subthreshold slope by reducing the fin width and increasing the fin numbers is known the optimized device design guideline in junctionless MuGFETs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.1-7
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• 2008

In this work, a two dimensional, self-consistent Poisson-$Schr{\ddot{o}}dinger$ solver has been implemented to study C-V characteristics in nanometer scale MuGFETs with considering quantum effects. The quantum-mechanical effects on gate-channel capacitance for different device dimension and gate configurations of nanometer scale MuGFETs have been analyzed. It has been found that 4he gate-channel capacitance per unit gate area is increased as the device dimension decreases. For different gate configurations, the gate-channel capacitance is decreased with increase of effective gate number. Those resu1ts have been explained by the distribution profile of electron concentration in the silicon surface and inversion capacitance. The length of inversion-layer centroid has been calculated from inversion capacitance with device dimension and gate configurations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.9
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• pp.2133-2138
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• 2013

In this paper, the variation of a steep subthreshold slope at elevated temperature in nanowire n-channel junctionless and inversion mode MuGFETs has been compared. It has been observed that the subthreshold slopes are increased with the increase of the operation temperature in junctionless and inversio-mode transistors. The variation of a subthreshold slope with operation temperature is more significant in junctionless transistor than inversion-mode transistor. The temperature dependence on the variation of a subthreshold slope for different fin widths shows a similar behavior regardless of fin width. From the temperature dependence on the variation of a subthreshold slope for different substrate biases, it has been observed that the variation of a subthreshold slope is less significant when the substrate bias was applied. It is worth noting that one can achieve a subthreshold slope of below 41mV/dec at elevated temperature of 400K using the junctionless MuGFETs with a positive substrate bias.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.1
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• pp.8-14
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• 2012

The device performances of n-channel MuGFET with different fin numbers and fin widths but the total effective channel width is constant have been characterized. Two kinds of Pi-gate devices with fin number=16, fin width=55nm, and fin number=14, fin width=80nm have been used in characterization. The threshold voltage, effective electron mobility, threshold voltage roll-off, inverse subthreshold slope, PBTI, hot carrier degradation, and drain breakdown voltage have been characterized. From the measured results, the short channel effects have been reduced for narrow fin width and large fin numbers. PBTI degradation was more significant in devices with large fin number and narrow fin width but hot carrier degradation was similar for both devices. The drain breakdown voltage was higher for devices with narrow fin width and large fin numbers. With considering the short channel effects and device degradation, the devices with narrow fin width and large fin numbers are desirable in the device layout of MuGFETs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.151-157
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• 2013

In this paper, a comparative analysis of PBTI induced device degradation in nanowire n-channel junctionless and inversion mode Multiple-Gate MOSFET(MuGFETs) has been performed. It has been observed that the threshold voltage is increased after PBTI stress and the threshold voltage variation of junctionless device is less significant than that of inversion mode device. However the degradation rate of junctionless device is less significant than that of inversion mode device. The activation energy of the device degradation is larger in inversion mode device than junctionless device. In order to analyze the more significant PBTI induced device degradation in inversion mode device than junctionless device, 3-dimensional device simulation has been performed. The electron concentration in inversion mode device is equal to the one in junctionless device but the electric field in inversion mode device is larger than junctionless device.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.7
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• pp.1657-1662
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• 2014

In this paper, the impact of substrate bias($V_{BS}$) on the zero capacitor RAM(Z-RAM) in n-channel junctionless multiple gate MOSFET(MuGFET) has been analyzed experimentally. Junctionless transistors with fin width of 50nm and 1 fin exhibits a memory window of 0.34V and a sensing margin of $1.8{\times}10^4$ at $V_{DS}=3.5V$ and $V_{BS}=0V$. As the positive $V_{BS}$ is applied, the memory window and sensing margin were improved due to an increase of impact ionization. When $V_{BS}$ is increased from 0V to 10V, not only the memory window is increased from 0.34V to 0.96V but also sensing margin is increased slightly. The sensitivity of memory window with different $V_{BS}$ in junctionless transistor was larger than that of inversion-mode transistor. A retention time of junctionless transistor is better than that of inversion-mode transistor due to low Gate Induced Drain Leakage(GIDL) current. To evaluate the device reliability of Z-RAM, the shifts in the Set/Reset voltages and current were measured.