• ETRI Journal
• /
• 제17권4호
• /
• pp.1-12
• /
• 1996

A novel body-tied silicon-on-insulator(SOI) n-channel metal-oxide-semiconductor field-effect transistor with grounded body electrode named GBSOI nMOSFET has been developed by wafer bonding and etch-back technology. It has no floating body effect such as kink phenomena on the drain current curves, single-transistor latch and drain current overshoot inherent in a normal SOI device with floating body. We have characterized the interface trap density, kink phenomena on the drain current ($I_{DS}-V_{DS}$) curves, substrate resistance effect on the $I_{DS}-V_{DS}$ curves, subthreshold current characteristics and single transistor latch of these transistors. We have confirmed that the GBSOI structure is suitable for high-speed and low-voltage VLSI circuits.

• Carbon letters
• /
• 제13권1호
• /
• pp.17-22
• /
• 2012

Currently, graphene is a topic of very active research in fields from science to potential applications. For various radio-frequency (RF) circuit applications including low-noise amplifiers, the unique ambipolar nature of graphene field-effect transistors can be utilized for high-performance frequency multipliers, mixers and high-speed radiometers. Potential integration of graphene on Silicon substrates with complementary metal-oxide-semiconductor compatibility would also benefit future RF systems. The future success of the RF circuit applications depends on vertical and lateral scaling of graphene metal-oxide-semiconductor field-effect transistors to minimize parasitics and improve gate modulation efficiency in the channel. In this paper, we highlight recent progress in graphene materials, devices, and circuits for RF applications. For passive RF applications, we show its transparent electromagnetic shielding in Ku-band and transparent antenna, where its success depends on quality of materials. We also attempt to discuss future applications and challenges of graphene.

• Transactions on Electrical and Electronic Materials
• /
• 제12권1호
• /
• pp.7-10
• /
• 2011

High voltage (HV) integrated circuits are viable alternatives to discrete circuits in a wide variety of applications. A HV device generally used in these circuits is a lateral double diffused metal oxide semiconductor (LDMOS) transistor. Attempts to model LDMOS devices are complicated by the existence of the lightly doped drain and by the extension of the poly-silicon and the gate oxide. Several physically based investigations of the bias-dependent drift resistance of HV devices have been conducted, but a complete physical model has not been reported. We propose a new technique to model HV devices using both the BSIM3 SPICE model and a bias dependent resistor model (sub-circuit macro model).

• EDISON SW 활용 경진대회 논문집
• /
• 제3회(2014년)
• /
• pp.434-438
• /
• 2014

CMOS의 최종형태로써 Gate-All-Around(GAA) Silicon Nanowire(NW)가 각광받고 있다. 이 논문에서 NW FET(Field Effect Transistor)의 채널 길이와 NW의 폭과 같은 size에 따른 특성변화를 실제 실험 data와 NW FET 특성분석 simulation을 이용해서 비교해보았다. MOSFET(Metal Oxide Semiconductor Field Effect Transistor)의 소형화에 따른 쇼트 채널 효과(short channel effect)에 의한 threshold voltage($V_{th}$), Drain Induced Barrier Lowering(DIBL), subthreshold swing(SS) 또한 비교하였다. 이에 더하여, 기존의 상용툴로 NW를 해석한 시뮬레이션 결과와도 비교해봄으로써 NW의 size scaling에 대한 EDISON NW 해석 simulation의 정확도를 파악해보았다.

• 한국전기전자재료학회논문지
• /
• 제28권11호
• /
• pp.698-703
• /
• 2015

In this study, we fabricated the dual gate (DG) ion-sensitive field-effect-transistor (ISFET) with flexible polyimide (PI) extended gate (EG). The DG ISFETs significantly enhanced the sensitivity of pH in electrolytes from 60 mV/pH to 1152.17 mV/pH and effectively improved the drift and hysteresis phenomenon. This is attributed to the capacitive coupling effect between top gate and bottom gate insulators of the channel in silicon-on-transistor (SOI) metal-oxide-semiconductor (MOS) FETs. Accordingly, it is expected that the PI-EG based DG-ISFETs is promising technology for high-performance flexible biosensor applications.

• 전기전자학회논문지
• /
• 제19권4호
• /
• pp.514-519
• /
• 2015

본 논문에서는 이중 게이트 junctionless MOSFET 의 성능 최적화를 위하여 다중 게이트 형태를 적용하여 평가한다. 금속 게이트들 사이의 일함수가 서로 다르므로 다중 게이트 구조를 적용할 경우 금속게이트 길이에 따라 소스와 드레인 주변의 전위를 조절할 수 있다. 동작 전류와 누설 전류 그리고 동작 전압은 게이트 구조에 의해 조절이 가능하며 이로 인한 동작 특성 최적화가 가능하다. 본 연구에서는 반도체 소자 시뮬레이션을 통하여 junctionless MOSFET 의 최적화를 구현하고 분석하는 연구를 수행 한다.

• 전기학회논문지
• /
• 제66권10호
• /
• pp.1494-1498
• /
• 2017

In this study, we investigate the influence of an overlap between the gate and source/drain regions of silicon nanowire (SiNW) CMOS (complementary metal-oxide-semiconductor) inverter on bendable plastic substrates and describe their electrical characteristics. The combination of n-channel silicon nanowire field-effect transistor (n-SiNWFET) and p-channel silicon nanowire field-effect transistor (p-SiNWFET) operates as an inverter logic gate. The gains with a drain voltage ($V_{dd}$) of 1 V are 3.07 and 1.21 for overlapped device and non-overlapped device, respectively. The superior electrical characteristics of each of the SiNW transistors including steep subthreshold slopes and the high $I_{on}/I_{off}$ ratios are major factors that enable the excellent operation of the logic gate.

• 한국전기전자재료학회논문지
• /
• 제28권11호
• /
• pp.683-689
• /
• 2015

For the formation of $N^+$ doping, the antimony ions are mainly used for the fabrication of a BJT (bipolar junction transistor), CMOS (complementary metal oxide semiconductor), FET (field effect transistor) and BiCMOS (bipolar and complementary metal oxide semiconductor) process integration. Antimony is a heavy element and has relatively a low diffusion coefficient in silicon. Therefore, antimony is preferred as a candidate of ultra shallow junction for n type doping instead of arsenic implantation. Three-dimensional (3D) profiles of antimony are also compared one another from different tilt angles and incident energies under same dimensional conditions. The diffusion effect of antimony showed ORD (oxygen retarded diffusion) after thermal oxidation process. The interfacial effect of a $SiO_2/Si$ is influenced antimony diffusion and showed segregation effects during the oxidation process. The surface sputtering effect of antimony must be considered due to its heavy mass in the case of low energy and high dose conditions. The range of antimony implanted in amorphous and crystalline silicon are compared each other and its data and profiles also showed and explained after thermal annealing under inert $N_2$ gas and dry oxidation.

• 한국정보통신학회:학술대회논문집
• /
• 한국정보통신학회 2022년도 추계학술대회
• /
• pp.115-117
• /
• 2022

피드백 전계 효과 트랜지스터(feedback field-effect transistor; FBFET)로 구성된 모놀리식 3차원 정적 랜덤 액세스 메모리(monolithic 3-dimensional static random access memory; M3D-SRAM)에 대해 TCAD(technology computer-aided design) 프로그램을 사용하여 전기적 특성을 조사하였다. FBFET로 구성된 M3D-SRAM(M3D-SRAM-FBFET)는 FDSOI(fully depleted silicon on insulator) 구조의 N형 FBFET와 N형 MOSFET(metal oxide semiconductor field effect transistor)로 이루어져 있으며 각각 하부와 상부에 위치한다. M3D-SRAM-FBFET의 메모리 동작 시, 공급 전압이 1.9 V에서 감소함에 따라 읽기 전류가 낮아졌으며, 공급 전압이 1.6 V 일 때 읽기 전류가 약 10배 감소하였다.

• Journal of Electrical Engineering and Technology
• /
• 제8권6호
• /
• pp.1497-1502
• /
• 2013

Recently, the junctionless (JL) transistors realized by a single-type doping process have attracted attention instead of the conventional metal-oxide-semiconductor field-effect transistors (MOSFET). The JL transistor can overcome MOSFET's problems such as the thermal budget and short-channel effect. Thus, the JL transistor is considered as great alternative device for a next generation low standby power silicon system. In this paper, the JL FinFET was simulated with a three dimensional (3D) technology computer-aided design (TCAD) simulator and optimized for DC characteristics according to device dimension and doping concentration. The design variables were the fin width ($W_{fin}$), fin height ($H_{fin}$), and doping concentration ($D_{ch}$). After the optimization of DC characteristics, RF characteristics of JL FinFET were also extracted.