Characteristics of Nanowire CMOS Inverter with Gate Overlap |
Yoo, Jeuk
(Dept. of Electrical Engineering, Korea University)
Kim, Yoonjoong (Dept. of Electrical Engineering, Korea University) Lim, Doohyeok (Dept. of Electrical Engineering, Korea University) Kim, Sangsig (Dept. of Electrical Engineering, Korea University) |
1 | J. A. Rogers and Z. Bao, "Printed plastic electronics and paperlike displays", J. Polym. Sci. Part A Polym. Chem., vol. 40, no. 20, pp. 3327-3334, August 2002. DOI |
2 | W. S. Wong and A. Salleo, eds, Flexible electronics: materials and applications, Vol. 11. Springer Science & Business Media, pp. 1-24, 2009. |
3 | M. Lee, Y. Jeon, T. Moon, and S. Kim, "Top-down fabrication of fully CMOS-compatible silicon nanowire arrays and their integration into CMOS inverters on plastic," ACS Nano, vol. 5, no. 4, pp. 2629-2636, February 2011. DOI |
4 | Y. Jeon, M. Lee, M. Kim, Y. Kim, and S. Kim, "Lowpower functionality of silicon-nanowire-assembled inverters on bendable plastics," Nano Res., vol. 9, no. 5, pp. 1409-1417, September 2016. DOI |
5 | J. Yun et al., "Nanowatt power operation of silicon nanowire NAND logic gates on bendable substrates," Nano Res., vol. 9, no. 12, pp. 3656-3662, December 2016. DOI |
6 | E. A. Chung, J. Koo, M. Lee, D. Y. Jeong, and S. Kim, "Enhancement-mode silicon nanowire field-effect transistors on plastic substrates," Small, vol. 5, no. 16, pp. 1821-1824, April 2009. DOI |
7 | C. H. Lee, D. R. Kim, and X. Zheng, "Fabricating nanowire devices on diverse substrates by simple transfer-printing methods," Proc. Natl. Acad. Sci., vol. 107, no. 22, pp. 9950-9955, April 2010. DOI |
8 | D. Wang, "Development of Ultra-High Density Silicon Nanowire Arrays for Electronics Applications," July 2008. |
9 | J. Appenzeller, J. Knoch, M. T. Bjork, H. Riel, H. Schmid, and W. Riess, "Toward nanowire electronics," IEEE Trans. Electron Devices, vol. 55, no. 11, pp. 2827-2845, November 2008. DOI |
10 | B. A. Sheriff, D. Wang, K. J. R. Heath, and J. N. Kurtin, "Complementary Symmetry Nanowire Logic Circuits : Experimental," vol. 2, no. 9, pp. 1789-1798, August 2008. DOI |
11 | H. Oh, K. Cho, and S. Kim, "Electrical characteristics of a bendable a-Si:H thin film transistor with overlapped gate and source/drain regions," Appl. Phys. Lett., vol. 110, no. 9, p. 93502, February 2017. DOI |
12 | R. Izawa, T. Kure, and E. Takeda, "Impact of the Gate-Drain Overlapped Device (GOLD) for Deep Submicrometer VLSI," IEEE Trans. Electron Devices, vol. 35, no. 12, pp. 2088-2093, December 1988. DOI |
13 | M. Liu, M. Cai, B. Yu, and Y. Taur, "Effect of gate overlap and source/drain doping gradient on 10-nm CMOS performance," IEEE Trans. Electron Devices, vol. 53, no. 12, pp. 3146-3149, December 2006. DOI |
14 | R. G. Gordon, D. Hausmann, E. Kim, and J. Shepard, "A kinetic model for step coverage by atomic layer deposition in narrow holes or trenches," Chem. Vap. Depos., vol. 9, no. 2, pp. 73-78, March 2003. DOI |
15 | A. M. Stoneham, "Why model high-k dielectrics?," J. Non. Cryst. Solids, vol. 303, no. 1, pp. 114-122, May 2002. DOI |
16 | G. Jo, W. K. Hong, J. Maeng, M. Choe, W. Park, and T. Lee, "Logic inverters composed of controlled depletionmode and enhancement-mode ZnO nanowire transistors," Appl. Phys. Lett., vol. 94, no. 17, pp. 1-4, April 2009. |