전기전자학회논문지 (Journal of IKEEE)

  • 제19권4호
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  • Pages.514-519
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  • 2015
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  • 1226-7244(pISSN)
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  • 2288-243X(eISSN)
한국전기전자학회 (Institute of Korean Electrical and Electronics Engineers)
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이중게이트 구조의 Junctionless FET 의 성능 개선에 대한 연구

Development of Gate Structure in Junctionless Double Gate Field Effect Transistors

  • Cho, Il Hwan (Dept. of Electronic Engineering, Myongji University) ;
  • Seo, Dongsun (Dept. of Electronic Engineering, Myongji University)
  • 투고 : 2015.11.20
  • 심사 : 2015.12.03
  • 발행 : 2015.12.31
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초록

본 논문에서는 이중 게이트 junctionless MOSFET 의 성능 최적화를 위하여 다중 게이트 형태를 적용하여 평가한다. 금속 게이트들 사이의 일함수가 서로 다르므로 다중 게이트 구조를 적용할 경우 금속게이트 길이에 따라 소스와 드레인 주변의 전위를 조절할 수 있다. 동작 전류와 누설 전류 그리고 동작 전압은 게이트 구조에 의해 조절이 가능하며 이로 인한 동작 특성 최적화가 가능하다. 본 연구에서는 반도체 소자 시뮬레이션을 통하여 junctionless MOSFET 의 최적화를 구현하고 분석하는 연구를 수행 한다.

We propose the multiple gate structure of double gate junctionless metal oxide silicon field oxide transistor (JL MOSFET) for device optimization. Since different workfunction within multiple metal gates, electric potential nearby source and drain region is modulated in accordance with metal gate length. On current, off current and threshold voltage are influenced with gate structure and make possible to meet some device specification. Through the device simulation work, performance optimization of double gate JL MOSFETs are introduced and investigated.

키워드

참고문헌

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