• JSTS:Journal of Semiconductor Technology and Science
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• 제1권3호
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• pp.189-192
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• 2001

A simple metal-insulator-metal (MIM) capacitor in a standard $0.25{\;}\mu\textrm{m}$ digital CMOS process is described. Using all six interconnect layers, this capacitor exploits both the lateral and vertical electrical fields to increase the capacitance density (capacitance per unit area). Compared to a conventional parallel plate capacitor in the four upper metal layers, this capacitor achieves lower parasitic substrate capacitance, and improves the capacitance density by a factor of 4. Measurements and an extracted model for the capacitor are also presented. Calculations, model and measurements agree very well.

• Transactions on Electrical and Electronic Materials
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• 제12권1호
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• pp.35-39
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• 2011

An electrically erasable programmable read-only memory (EEPROM) containing a stacked metal-insulator-metal (MIM) and n-well capacitor is proposed. It was fabricated using a 0.18 $\mu$m standard complementary metal-oxide semiconductor process. The depletion capacitance of the n-well region was effectively applied without sacrificing the cell-area and control gate coupling ratio. The device performed very similarly to the MIM capacitor cell regardless of the smaller cell area. This is attributed to the high control gate coupling ratio and capacitance. The erase speed of the proposed EEPROM was faster than that of the cell containing the MIM control gate.

• ETRI Journal
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• 제30권6호
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• pp.826-832
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• 2008

The metal-ferroelectric-metal (MFM) capacitor in the ferroelectric random access memory (FeRAM) embedded RFID chip is used in both the memory cell region and the peripheral analog and digital circuit area for capacitance parameter control. The capacitance value of the MFM capacitor is about 30 times larger than that of conventional capacitors, such as the poly-insulator-poly (PIP) capacitor and the metal-insulator-metal (MIM) capacitor. An MFM capacitor directly stacked over the analog and memory circuit region can share the layout area with the circuit region; thus, the chip size can be reduced by about 60%. The energy transformation efficiency using the MFM scheme is higher than that of the PIP scheme in RFID chips. The radio frequency operational signal properties using circuits with MFM capacitors are almost the same as or better than with PIP, MIM, and MOS capacitors. For the default value specification requirement, the default set cell is designed with an additional dummy cell.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2008년도 제34회 동계학술대회 초록집
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• pp.172-172
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• 2008

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 추계학술대회 논문집 학회본부
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• pp.333-335
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• 1997

This paper was performed to investigate the characteristic of the Pt-MIS(Metal Insulator Semiconductor) capacitor composed of the LPCVD nitride on the oxide for the hydrogen gas detection. Pt was used as catalytic metal for detecting the hydrogen gas and the flat band voltage shift was measured at various hydrogen concentration and catalytic metal thickness. We found the flat band voltage shift was proportional to the hydrogen concentration and catalytic metal thickness was little effect to the response time.

• 한국진공학회지
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• 제18권1호
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• pp.30-36
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• 2009

투명 전자소자의 고유전 $HfO_2$ 절연막을 개발하기 위하여, ITO/$HfO_2$/ITO 금속-절연체-금속 (Metal-Insulator-Metal, MIM) 커패시터 구조를 형성한후 $HfO_2$ 박막의 두께에 따른 전기적, 광학적, 구조적 특성의 변화를 연구하였다. $HfO_2$ 박막의 두께가 50 nm에서 300 nm로 증가함에 따라 유전상수는 20에서 10이하로 감소하였으나, $HfO_2$ 두께가 증가함에 따라 누설전류는 감소하여 200 nm 이상의 두께에서는 $2.7{\times}10^{-12}\;A/cm^2$ 이하의 낮은 누설전류 특성을 나타내었다. ITO/$HfO_2$/ITO MIM 커패시터의 $HfO_2$ 박막의 두께가 50 nm에서 300 nm로 증가함에 따라 투과율은 감소하였으나 300 nm 두께에서도 가시광선 영역에서 80% 이상의 투과율을 나타내어 우수한 투과도 특성을 나타내었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1061-1064
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• 2003

In this paper, we deposited A1$_2$O$_3$ thin film using atomic layer deposition(ALD) method on Ti and fabricated metal-insulator-metal(MIM) capacitor. In the result of this study, the typical deposition rate was about 1.12$\AA$/cycle. About 30 nm of Ti was consumed during deposition and TiO$_{x}$ was formed at the interface of A1$_2$O$_3$ and Ti. Its surface roughness was 1.54nm. The leakage current density was 1.5 nA/$\textrm{cm}^2$. The temperature coefficient of capacitance(TCC) of MIM capacitor was 41 ppm/$^{\circ}C$ at 1MHz and 100 ppm/$^{\circ}C$ at 100 kHz.z.

• 한국재료학회지
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• 제17권11호
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• pp.574-579
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• 2007

Amorphous $BaTi_4O_9$ ($BT_4$) film was deposited on Pt/Si substrate by RF magnetron sputter and their dielectric properties and electrical properties are investigated. A cross sectional SEM image and AFM image of the surface of the amorphous $BT_4$ film deposited at room temperature showed the film was grown well on the substrate. The amorphous $BT_4$ film had a large dielectric constant of 32, which is similar to that of the crystalline $BT_4$ film. The leakage current density of the $BT_4$ film was low and a Poole-Frenkel emission was suggested as the leakage current mechanism. A positive quadratic voltage coefficient of capacitance (VCC) was obtained for the $BT_4$ film with a thickness of <70 nm and it could be due to the free carrier relaxation. However, a negative quadratic VCC was obtained for the films with a thickness ${\geq}96nm$, possibly due to the dipolar relaxation. The 55 nm-thick $BT_4$ film had a high capacitance density of $5.1fF/{\mu}m^2$ with a low leakage current density of $11.6nA/cm^2$ at 2 V. Its quadratic and linear VCCs were $244ppm/V^2$ and -52 ppm/V, respectively, with a low temperature coefficient of capacitance of $961ppm/^{\circ}C$ at 100 kHz. These results confirmed the potential suitability of the amorphous $BT_4$ film for use as a high performance metal-insulator-metal (MIM) capacitor.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.543-548
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• 2014

In this paper, the dielectric relaxation and reliability of high capacitance density metal-insulator-metal (MIM) capacitors using $Al_2O_3-HfO_2-Al_2O_3$ and $SiO_2-HfO_2-SiO_2$ sandwiched structure under constant voltage stress (CVS) are characterized. These results indicate that although the multilayer MIM capacitor provides high capacitance density and low dissipation factor at room temperature, it induces greater dielectric relaxation level (in ppm). It is also shown that dielectric relaxation increases and leakage current decreases as functions of stress time under CVS, because of the charge trapping effect in the high-k dielectric.

• 한국전자통신학회논문지
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• 제9권7호
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• pp.747-752
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• 2014

본 논문은 $0.13{\mu}m$ 기술의 디자인을 10% 축소하는데 기존의 로직 디바이스만의 축소와는 달리 로직뿐 아니라 입, 출력 회로의 축소에 관한 것이다. 게이트 산화막(1.2V)을 decoupled plasma nitridation(DPN) oxide로 변경함으로써 flicker 노이즈를 축소 전 공정에 비해 1/3-1/5배 감소됨을 확인하였다. 또한, 축소에 의한 피할 수 없는 문제는 일반적인 metal insulator metal(MIM)의 캐패시터 문제이다. 이를 해결하기 위하여 20% 높은 MIM 캐패시터($1.2fF/{\mu}m^2$)를 개선하고 그 특성을 평가하였다.