• 한국표면공학회지
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• 제35권3호
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• pp.127-132
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• 2002

High speed performance of ferroelectric Pb(Zr,Ti)$O_3$ (PZT) based capacitors is reported. La substitution up to 10% was performed to systematically lower the coercive and saturation voltages of epitaxial ferroelectric capacitors grown on Si using a ($Ti_{0.9}$ /$Al_{0.1}$ )N/Pt conducting barrier composite. Ferroelectric capacitors substituted with 10% La show significantly lower coercive voltage compared to capacitors with 0% and 3% La. This is attributed to a systematic decrease in the tetragonality (i.e., c/a ratio) of the ferroelectric phase. Furthermore, the samples doped with 10% La showed dramatically better retention and pulse width dependent polarization compared to the capacitors with 0% and 3% La. These capacitors show promise as storage elements in low power high density memory architectures.

• 한국결정성장학회지
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• 제12권3호
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• pp.157-160
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• 2002

The ferroelectric domain variation and electrical performance of $Pb(Zr,Ti)O_{3}$ (PZT) based capacitors through La additions were systematically studied. La substitution up to 10 % was performed to lower the coercive and saturation voltages of epitaxial ferroelectric capacitors grown on Si using a (Ti_{0.9}Al_{0.1})N/Pt$ conducting barrier composite. Ferroelectric capacitors substituted with 10 % La show significantly lower coercive voltage compared to capacitors with 0 % and 3 % La. This is attributed to a systematic microstructure change into $180^{\circ}C$ domain and decrease in the tetragonality (i.e., c/a ratio) of the ferroelectric phase. These capacitors show promise as storage elements in low power memory architectures.

• Transactions on Electrical and Electronic Materials
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• 제15권1호
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• pp.16-19
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• 2014

Charge trapping nonvolatile memory capacitors with $ZrO_2$ as charge trapping layer were fabricated, and the effects of post annealing atmosphere ($NH_3$ and $N_2$) on their memory storage characteristics were investigated. It was found that the memory windows were improved, after annealing treatment. The memory capacitor after $NH_3$ annealing treatment exhibited the best electrical characteristics, with a 6.8 V memory window, a lower charge loss ~22.3% up to ten years, even at $150^{\circ}C$, and excellent endurance (1.5% memory window degradation). The results are attributed to deep level bulk charge traps, induced by using $NH_3$ annealing.

• 한국결정성장학회지
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• 제12권3호
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• pp.161-164
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• 2002

Polycrystalline and epitaxial heterostructure films of $La_{0.5}Sr_{0.5}CoO_{3}/Pb(Nb_{0.04}Zr_{0.28}Ti_{0.68})O_{3}/La_{0.5}Sr_{0.5}CoO_{3}$ (LSCO/PNZT/LSCO) capacitors were evaluated in terms of low voltage and high speed operation in high density memory, using TiN/Pt conducting barrier combination. Structural studies for a high density ferroelectric memory process flow, which requires the integration of conducting barrier layers to connect the drain of the pass-gate transistor to the bottom electrode of the ferroelectric stack, indicate complete phase purity (i.e. fully perovskite) in both epitaxial and polycrystalline materials. The polycrystalline capacitors show lower remnant polarization and coercive voltages. However, the retention, and high-speed characteristics are similar, indicating minimal influence of crystalline quality on the ferroelectric properties.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권4호
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• pp.257-263
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• 2006

New charge pump circuits with low area and high power efficiency are proposed and verified in this paper. These pump circuits do not suffer the voltage stress higher than $V_{DD}$ across their pumping capacitors. Thus they can use the thin-oxide MOSFETs as the pumping capacitors. Using the thin-oxide capacitors can reduce the area of charge pumps greatly while keeping their driving capability. Comparing the new pump (NCP-2) with the conventional pump circuit using the thick-oxide capacitors shows that the power efficiency of NCP-2 is the same with the conventional one but the area efficiency of NCP-2 is improved as much as 71.8% over the conventional one, when the $V_{PP}/V_{DD}$ ratio is 3.5 and $V_{DD}$=1.8V.

• ETRI Journal
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• 제30권6호
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• pp.826-832
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• 2008

The metal-ferroelectric-metal (MFM) capacitor in the ferroelectric random access memory (FeRAM) embedded RFID chip is used in both the memory cell region and the peripheral analog and digital circuit area for capacitance parameter control. The capacitance value of the MFM capacitor is about 30 times larger than that of conventional capacitors, such as the poly-insulator-poly (PIP) capacitor and the metal-insulator-metal (MIM) capacitor. An MFM capacitor directly stacked over the analog and memory circuit region can share the layout area with the circuit region; thus, the chip size can be reduced by about 60%. The energy transformation efficiency using the MFM scheme is higher than that of the PIP scheme in RFID chips. The radio frequency operational signal properties using circuits with MFM capacitors are almost the same as or better than with PIP, MIM, and MOS capacitors. For the default value specification requirement, the default set cell is designed with an additional dummy cell.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.147-148
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• 2006

Ge nanocrystals(NCs)-embedded MOS capacitors are charactenzed in this work using capacitance-voltage measurement. High-k dielectrics $HfO_2$ are employed for the gate material m the MOS capacitors, and the C-V curves obtained from $O_2-$ and $NH_3$-annealed $HfO_2$ films are analyzed.

• 한국전기전자재료학회논문지
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• 제17권12호
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• pp.1283-1288
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• 2004

Metal-ferroelectric-insulator-semiconductor(WFIS) capacitors using rapid thermal annealed LiNbO$_3$/AlN/Si(100) structure were fabricated and demonstrated nonvolatile memory operations. The capacitors on highly doped Si wafer showed hysteresis behavior like a butterfly shape due to the ferroelectric nature of the LiNbO$_3$ films. The typical dielectric constant value of LiNbO$_3$ film in the MFIS device was about 27, The gate leakage current density of the MFIS capacitor was 10$^{-9}$ A/cm$^2$ order at the electric field of 500 kV/cm. The typical measured remnant polarization(2P$_{r}$) and coercive filed(Ec) values were about 1.2 $\mu$C/cm$^2$ and 120 kV/cm, respectively The ferroelectric capacitors showed no polarization degradation up to 10$^{11}$ switching cycles when subjected to symmetric bipolar voltage pulses of 1 MHz. The switching charges degraded only by 10 % of their initial values after 4 days at room temperature.e.

• Transactions on Electrical and Electronic Materials
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• 제13권3호
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• pp.162-164
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• 2012

In this study, we fabricate Pt nanoparticle (NP)-embedded MOS capacitors at room temperature and investigate their memory characteristics. The Pt NPs are separated from each other and situated between the tunnel and control oxide layers. The average size and density of the Pt NPs are 4 nm and $3.2{\times}10^{12}cm^{-2}$, respectively. Counterclockwise hysteresis with a width of 3.3 V is observed in the high-frequency capacitance-voltage curve of the Pt NP-embedded MOS capacitor. Moreover, more than 93% of the charge remains even after $10^4$ s.

• Transactions on Electrical and Electronic Materials
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• 제15권5호
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• pp.241-244
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• 2014

Charge trap flash memory capacitors incorporating $(HfO_2)_x(Al_2O_3)_{1-x}$ film, as the charge trapping layer, were fabricated. The effects of the charge trapping layer composition on the memory characteristics were investigated. It is found that the memory window and charge retention performance can be improved by adding Al atoms into pure $HfO_2$; further, the memory capacitor with a $(HfO_2)_{0.9}(Al_2O_3)_{0.1}$ charge trapping layer exhibits optimized memory characteristics even at high temperatures. The results should be attributed to the large band offsets and minimum trap energy levels. Therefore, the $(HfO_2)_{0.9}(Al_2O_3)_{0.1}$ charge trapping layer may be useful in future nonvolatile flash memory device application.