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Charge Pump Circuits with Low Area and High Power Efficiency for Memory Applications  

Kang, Kyeong-Pil (School of Electrical Engineering, Kookmin University)
Min, Kyeong-Sik (School of Electrical Engineering, Kookmin University)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.6, no.4, 2006 , pp. 257-263 More about this Journal
Abstract
New charge pump circuits with low area and high power efficiency are proposed and verified in this paper. These pump circuits do not suffer the voltage stress higher than $V_{DD}$ across their pumping capacitors. Thus they can use the thin-oxide MOSFETs as the pumping capacitors. Using the thin-oxide capacitors can reduce the area of charge pumps greatly while keeping their driving capability. Comparing the new pump (NCP-2) with the conventional pump circuit using the thick-oxide capacitors shows that the power efficiency of NCP-2 is the same with the conventional one but the area efficiency of NCP-2 is improved as much as 71.8% over the conventional one, when the $V_{PP}/V_{DD}$ ratio is 3.5 and $V_{DD}$=1.8V.
Keywords
charge pump; power efficiency; area efficiency; memory; DRAM;
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1 P. Favrat, P. Deval, and M. Declercq, 'A high-efficiency CMOS voltage doubler,' IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 410-416, March 1998   DOI   ScienceOn
2 J.-T. Wu and K.-L. Chang, 'MOS charge pumps for low-voltage operation,' IEEE J. Solid-State Circuits, vol. 33, no. 4, pp. 592-597, April 1998   DOI   ScienceOn
3 K.-P. Kang and K.-S. Min, 'Area-efficient charge pump for memory applications,' International SoC Design Conference, vol. 1, pp. 141-144, Seoul in Korea, October 2006
4 J. F. Dickson, 'On-chip high-voltage generation in NMOS integrated circuits using an improved voltage multiplier technique,' IEEE J. Solid-State Circuits, vol. 11, pp. 374-378, June 1976   DOI
5 K.-S. Min and J.-H. Ahn, 'CMOS charge pumps using cross-coupled charge transfer switches with improved voltage pumping gain and low gate-oxide stress for low-voltage memory circuits,' IEICE Trans. Electronics, vol. E85-C, no. 1, pp. 225-229, January 2002