• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.379-380
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• 2008

This paper presents a wafer-level package using a Dry Film Resist(DFR) for RF MEMS devices. Vertical interconnection is made through the hole formed on the glass cap. Bonding using the DFR has not only less effects on the surface roughness but also low process temperature. We used DFR as adhesive polymer and made the vertical interconnection through Au electroplating. Therefore, we developed a wafer-level package that is able to be used in RF MEMS devices and vertical interconnection.

• 센서학회지
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• 제15권1호
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• pp.58-64
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• 2006

In this study, we describe a low-temperature wafer-level thermocompression bonding using electroplated gold seal line and bonding pads by electroplating method for RF-MEMS devices. Silicon wafers, electroplated with gold (Au), were completely bonded at $320^{\circ}C$ for 30 min at a pressure of 2.5 MPa. The through-hole interconnection between the packaged devices and external terminal did not need metal filling process and was made by gold films deposited on the sidewall of the throughhole. This process was low-cost and short in duration. Helium leak rate, which is measured to evaluate the reliability of bonded wafers, was $2.7{\pm}0.614{\times}10^{-10}Pam^{3}/s$. The insertion loss of the CPW packaged was $-0.069{\sim}-0.085\;dB$. The difference of the insertion loss between the unpackaged and packaged CPW was less than -0.03. These values show very good RF characteristics of the packaging. Therefore, gold thermocompression bonding can be applied to high quality hermetic wafer level packaging of RF-MEMS devices.

• 한국기계가공학회지
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• 제14권6호
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• pp.104-110
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• 2015

LED has added value as a lighting source in the illuminating industry because of its high efficiency and low power consumption. In LED production processes, the chip cutting process, which mainly uses a scribing process with a laser has an effect on quality and productivity of LED. This scribing process causes problems like heat deformation, decreasing strength. The inner laser method, which makes a void in wafer and induces self-cracking, can overcome these problems. In this paper, cutting sapphire wafer for fabricating LED chip using the inner laser scribing process is proposed and evaluated. The aim is to settle basic experiment conditions, determine parameters of cutting, and analyze the characteristics of cutting by means of experimentation.

• 한국전기전자재료학회논문지
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• 제25권5호
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• pp.353-360
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• 2012

As semiconductor device technology continuously shrinks, low-open area etch process prevails in front-end etch process, such as contact etch as well as one cylindrical storage (OCS) etch. To eliminate over loaded wafer processing test, it is commonly performed to emply diced small coupons at stage of initiative process development. In nominal etch condition, etch responses of whole wafer test and coupon test may be regarded to provide similar results; however, optical emission spectroscopy (OES) which is frequently utilize to monitor etch chemistry inside the chamber cannot be regarded as the same, especially etch mask is not the same material with wafer chuck. In this experiment, we compared OES data acquired from two cases of etch experiments; one with coupon etch tests mounted on photoresist coated wafer and the other with coupons only on the chuck. We observed different behaviors of OES data from the two sets of experiment, and the analytical results showed that careful investigation should be taken place in OES study, especially in coupon size etch.

• 한국결정성장학회지
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• 제15권1호
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• pp.34-38
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• 2005

Langasite 단결정 wafer의 chemical mechanical planarization 공정에서 pH level 및 slurry 입도가 가공속도 및 평탄화도에 미치는 영향을 조사하였다. 낮은 pH level 조건하에서 더 높은 가공속도 값이 얻어진 반면에 평탄화도는 colloidal silica slurry의 평균입경에 의해 좌우됨을 확인하였다. 0.045 ㎛의 비정질 silica 입자를 함유한 슬러리를 사용하였을 때 표면에 잔류 scratch 형성이 없이 가장 좋은 가공성을 확보할 수 있었다. 가공속도와 평탄화도는 effective particle number에 대한 강한 의존성을 나타내었으며, effective particle number가 낮은 조건하에서 가공속도는 더 낮은 분포를 나타내었으나 평탄화도는 더 우수한 경향성을 확인하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 C
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• pp.1648-1650
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• 1996

In present paper, Cu films $4{\mu}m$, thick were fabricated by dual deposition methods using RF magnetron sputtering on Si wafer. The dependence of the electrical resistivity, adherence, and reflection in Cu films [$Cu_{4-x}$(low resistivity) / $Cu_x$(high adherence) / Si- wafer] on the x thickness have been investigated. Cu films of $4{\mu}m$ thickness formed with dual deposition methods had the low electrical resistivity of about $2.6{\mu}{\Omega}{\cdot}cm$ and high adherence of about 700g/cm. In conclusion, it is possible for these films to be used for micro-devices.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.433-433
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• 2012

As the requirement in patterning geometry continuously shrinks down, the termination of etch process at the exact time became crucial for the success in nano patterning technology. By virtue of real-time optical emission spectroscopy (OES), etch end point detection (EPD) technique continuously develops; however, it also faced with difficulty in low open ratio etching, typically in self aligned contact (SAC) and one cylinder contact (OCS), because of very small amount of optical emission from by-product gas species in the bulk plasma glow discharge. In developing etching process, one may observe that coupon test is being performed. It consumes costs and time for preparing the patterned sample wafers every test in priority, so the coupon wafer test instead of the whole patterned wafer is beneficial for testing and developing etch process condition. We also can observe that etch open area is varied with the number of coupons on a dummy wafer. However, this can be a misleading in OES study. If the coupon wafer test are monitored using OES, we can conjecture the endpoint by experienced method, but considering by data, the materials for residual area by being etched open area are needed to consider. In this research, we compare and analysis the OES data for coupon wafer test results for monitoring about the conditions that the areas except the patterns on the coupon wafers for real-time process monitoring. In this research, we compared two cases, first one is etching the coupon wafers attached on the carrier wafer that is covered by the photoresist, and other case is etching the coupon wafers on the chuck. For comparing the emission intensity, we chose the four chemical species (SiF2, N2, CO, CN), and for comparing the etched profile, measured by scanning electron microscope (SEM). In addition, we adopted the Dynamic Time Warping (DTW) algorithm for analyzing the chose OES data patterns, and analysis the covariance and coefficient for statistical method. After the result, coupon wafers are over-etched for without carrier wafer groups, while with carrier wafer groups are under-etched. And the CN emission intensity has significant difference compare with OES raw data. Based on these results, it necessary to reasonable analysis of the OES data to adopt the pre-data processing and algorithms, and the result will influence the reliability for relation of coupon wafer test and whole wafer test.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 학술대회지
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• pp.482-485
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• 2004

We fabricated a hybrid bulk/fully depleted silicon on insulator (FDSOI) complementary metal oxide semiconductor (CMOS) active pixel image sensor. The active pixel is comprised of reset and source follower transistors on the SOI seed wafer, while the pinned photodiode and readout gate and floating diffusion are fabricated on the SOI handle wafer after the removal of the buried oxide. The source of dark current is eliminated by hybrid bulk/FDSOI pixel structure between localized oxidation of silicon (LOCOS) and photodiode(PD). By using the low noise hybrid pixel structure, dark currents qm be suppressed significantly. The pinned photodiode can also be optimized for quantum efficiency and reduce the noise of dark current. The spectral response of the pinned photodiode on the SOI handle wafer is very flat between 400 nm and 700 nm and the dark current that is higher than desired is about 10 nA/cm2 at a $V_{DD}$ of 2 V.

• 전자공학회논문지
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• 제51권8호
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• pp.23-29
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• 2014

실리콘 태양전지 제조에 기판으로 사용되는 156 mm 실리콘 웨이퍼의 제작 공정에 있어서 제품 불량 및 성능 저하를 유발하는 웨이퍼 표면 오염원을 분석하였으며, 이를 제거하기 위한 오존수 세정에 대하여 실험하였다. 오염물질은 웨이퍼 절단 공정에서 사용되는 슬러리 및 세척액 속에 포함된 유기물과 소잉 와이어로부터 분리된 미세입자에 의해 형성되며, 오존수 세정공정을 통하여 제거할 수 있었다. 이 기술을 적용하면 태양전지용 웨이퍼를 저렴하고 효율적이며 친환경적으로 제조할 수 있다.

• 한국분말재료학회지
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• 제23권1호
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• pp.43-48
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• 2016

Waste SiC powders obtained from silicon wafer sludge have very low density and a narrow particle size distribution of $10-20{\mu}m$. A scarce yield of C and Si is expected when SiC powders are incorporated into the Fe melt without briquetting. Here, the briquetting variables of the SiC powders are studied as a function of the sintering temperature, pressure, and type and contents of the binders to improve the yield. It is experimentally confirmed that Si and C from the sintered briquette can be incorporated effectively into the Fe melt when the waste SiC powders milled for 30 min with 20 wt.% Fe binder are sintered at $1100^{\circ}C$ upon compaction using a pressure of 250 MPa. XRF-WDS analysis shows that an yield of about 90% is obtained when the SiC briquette is kept in the Fe melt at $1650^{\circ}C$ for more than 1 h.