• Proceedings of the KIEE Conference
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• 1999.07c
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• pp.1437-1439
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• 1999

This paper describes test method though low voltage power system implementation for high impedance fault relay test before its operation in real power system. Through this test, relay tested its function and algorithm. In this paper, we will provides test method using low voltage power system and its results.

• ETRI Journal
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• v.25 no.5
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• pp.321-327
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• 2003

Testing time and power consumption during the testing of SoCs are becoming increasingly important with an increasing volume of test data in intellectual property cores in SoCs. This paper presents a new algorithm to reduce the scan-in power and test data volume using a modified scan latch reordering algorithm. We apply a scan latch reordering technique to minimize the column hamming distance in scan vectors. During scan latch reordering, the don't-care inputs in the scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.7
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• pp.458-461
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• 2005

Power dissipated during test application is substantially higher than power dissipated during functional operation which can decrease the reliability and lead to yield loss. This paper presents a new technique for power minimization during test application in full scan sequential circuits. This paper shows freezing of combinational logic parts during scan shift operation in test mode. The freezing technique leads to power to minimization. Significant power reduction in the scan techniques is achieved on ISCAS 89 benchmarks.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.85-95
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• 2004

As the design complexity increases, it is a major problem that the size of test pattern is large and power consumption is high in scan, especially system-on-a-chip(SoC), with the automatic test equipment(ATE). Because static compaction of test patterns heads to higher power for testing, it is very hard to reduce the test pattern volume for low power testing. This paper proposes an efficient compression/decompression algorithm based on run-length coding for reducing the amount of test data for low power testing that must be stored on a tester and be transferred to SoC. The experimental results show that the new algorithm is very efficient by reducing the memory space for test patterns and the hardware overhead for the decoder.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.228-230
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• 2002

We present a new low power scan testing and test data compression method for System-On-a-Chip (SOC). The don't cares in unspecified scan vectors are mapped to binary values for low power and encoded by adaptive encoding method for higher compression. Also, the scan-in direction of scan vectors is determined for low power. Experimental results for full-scanned versions of ISCAS 89 benchmark circuits show that the proposed method has both low power and higher compression.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.961-963
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• 2000

Most of the application standard of the low-voltage devices have applied one the IEC standard another the UL standard. European union applied the IEC60947-1 standard has not exceed 1000V a.c. or 1500V d.c.. Therefore. it is necessary to the low-voltage device has expended for rated operational voltage with our products. The export of European market shall be made for the CE-Marking in accordance with IEC60947-1 ( Low-voltage switchgear and controlgear). We shall be considered for the requirement with the IEC standard. In this time to study for power supply system at EU ( European union. At that time for design and development in order to the construction and test method among the study for the rated insulation voltage at less then 690V.

• Nuclear Engineering and Technology
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• v.51 no.4
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• pp.1032-1036
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• 2019

When the equipment which is related to safety or important to power production is installed in nuclear power plant units (NPPs), verification of equipment Electromagnetic Susceptibility (EMS) must be performed. The low-frequency radiated magnetic field susceptibility (RS101) test is one of the EMS tests specified in U.S NRC (Nuclear Regulatory Commission) Regulatory Guide (RG) 1.180 revision 1. The RS101 test verifies the ability of equipment installed in close proximity to sources of large radiated magnetic fields to withstand them. However, RG 1.180 revision 1 allows for an exemption of the low-frequency radiated magnetic susceptibility (RS101) test if the safety-related equipment will not be installed in areas with strong sources of magnetic fields. There is no specific exemption criterion in RG 1.180 revision 1. EPRI TR-102323 revision 4 specifically provides a guide that the low-frequency radiated magnetic field susceptibility (RS101) test can be conservatively exempted for equipment installed at least 1 m away from the sources of large magnetic fields (>300 A/m). But there is no exemption criterion for equipment installed within 1 m of the sources of smaller magnetic fields (<300 A/m). Since some types of equipment radiating magnetic flux are often installed near safety related equipment in an electrical equipment room (EER) and main control room (MCR), the RS101 test exemption criterion needs to be reasonably defined for the cases of installation within 1 m. There is also insufficient data regarding the strength of magnetic fields that can be used in NPPs. In order to ensure confidence in the RS101 test exemption criterion, we measured the strength of low-frequency radiated magnetic fields by distance. This study is expected to provide an insight into the RS101 test exemption criterion that meets the RG 1.180 revision 1. It also provides a margin analysis that can be used to mitigate the influence of low-frequency radiated magnetic field sources in NPPs.

• The Journal of the Korea Contents Association
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• v.5 no.4
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• pp.188-196
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• 2005

This paper presents a new test data compression and low power scan test method that can reduce test time and power consumption. A proposed method can reduce the scan-in power and test data volume using a modified scan cell reordering algorithm and hybrid adaptive encoding method. Hybrid test data compression method uses adaptively the Golomb codes and run-length codes according to length of runs in test data, which can reduce efficiently the test data volume compare to previous method. We apply a scan cell reordering technique to minimize the column hamming distance in scan vectors, which can reduce the scan-in power consumption and test data. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases. The proposed method showed an about a 17%-26% better compression ratio, 8%-22% better average power consumption and 13%-60% better peak power consumption than that of previous method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.104-110
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• 2006

The huge test data volume, test time and power consumption are major problems in system-on-a-chip testing. To tackle those problems, we propose a new test data compression technique. Initially, don't-cares in a pre-computed test cube set are assigned to reduce the test power consumption, and then, the fully specified low-power test data is transformed to improve compression efficiency by neighboring bit-wise exclusive-or (NB-XOR) scheme. Finally, the transformed test set is compressed to reduce both the test equipment storage requirements and test application time.

• KEPCO Journal on Electric Power and Energy
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• v.7 no.1
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• pp.101-105
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• 2021

Encouragement of DER from Korean government with several policies boosts DER installation in power system. When the penetration of DER in the grid is getting high, loss of generation with break-away of DER by abnormal grid conditions should be considered, because loss of high generation causes abnormal low frequency and additional operations of protection system. Therefore, KEPCO where is Korean power utility is preparing improvement in regulations for DERs connected to the grid to support abnormal grid conditions such as low and high frequencies or voltages. This is called 'Ride Through' because the requirement is for DER to maintain grid connection during required periods when abnormal grid conditions occur. However, it is not easy to have a test for ride through capability in reality because emulation of abnormal grid conditions is not possible in real power system in operation. Also, it is not easy to have a study on grid effect when ride through capability fails with the same reason. PHILs (Power Hardware In the Loop System) makes it possible to analyze power system and hardware performance at once. Therefore, this paper introduces PHILs test methods and presents verification of ride through capability especially for low voltage grid conditions.