ETRI Journal

Electronics and Telecommunications Research Institute (한국전자통신연구원)
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Efficient Test Data Compression and Low Power Scan Testing in SoCs

  • Received : 2003.01.15
  • Published : 2003.10.31
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Abstract

Testing time and power consumption during the testing of SoCs are becoming increasingly important with an increasing volume of test data in intellectual property cores in SoCs. This paper presents a new algorithm to reduce the scan-in power and test data volume using a modified scan latch reordering algorithm. We apply a scan latch reordering technique to minimize the column hamming distance in scan vectors. During scan latch reordering, the don't-care inputs in the scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.

Keywords

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