Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

A new efficient algorithm for test pattern compression considering low power test in SoC

SoC환경에서의 저전력 테스트를 고려한 테스트 패턴 압축에 대한 효율적인 알고리즘

  • 신용승 (LG전자 System IC 사업담당) ;
  • 강성호 (연세대학교 전기전자공학과)
  • Published : 2004.09.01
Download PDF
⟨ Previous Next ⟩

Abstract

As the design complexity increases, it is a major problem that the size of test pattern is large and power consumption is high in scan, especially system-on-a-chip(SoC), with the automatic test equipment(ATE). Because static compaction of test patterns heads to higher power for testing, it is very hard to reduce the test pattern volume for low power testing. This paper proposes an efficient compression/decompression algorithm based on run-length coding for reducing the amount of test data for low power testing that must be stored on a tester and be transferred to SoC. The experimental results show that the new algorithm is very efficient by reducing the memory space for test patterns and the hardware overhead for the decoder.

최근 반도체 칩의 집적도가 올라가고 System-on-Chip(Soc)환경이 보편화되면서 Automatic Test Equipment(ATE)를 이용한 테스트 수행시 테스트 패턴의 크기 문제와 스캔체인에서의 전력 소모문제가 크게 부각되고 있다. 또한, 테스트 패턴 크기문제를 해결하기 위해 테스트 패턴을 압축하게 되면 테스트 패턴의 소모하는 전력량이 커지게 되어 저전력 테스트를 수행하는데 어려움이 있어 두 가지 문제를 해결할 수 없었다 본 논문에서는 이러한 문제점들을 동시에 해결하기 위해서 Run-length code를 기반으로 하여 저전력 테스트가 가능하면서 테스트 패턴의 크기도 줄일 수 있는 알고리즘을 제안하였다. 본 논문에서는 기존에 제시되었던 알고리즘과 비교ㆍ분석하는 실험을 통하여 이 알고리즘의 효율성을 보여주고 있다.

Keywords

References

  1. Y. Zorian, 'A distributed BIST control scheme for complex VLSI devices,' Proc. of IEEE VLSI Test Symp., 1993, pp4-9 https://doi.org/10.1109/VTEST.1993.313316
  2. R.M. Chou, K. K. Saluja, and V.D. Agrawal, 'Scheduling test for VLSI systems under power constraints,' IEEE Trans. VLSI Syst., vol 5, pp.175-l85, June 1997 https://doi.org/10.1109/92.585217
  3. S.Wang and S.K. Gupta, 'LT-RTPG: A new test-per-scan BIST TPG for low heat disspation,' Proc. of Int. Test. Conf., 1990, pp. 84-94 https://doi.org/10.1109/TEST.1999.805617
  4. S.Gerstendorfer and H.J. Wunderlich, 'Minimized power consumption for scan-based BIST,' Proc. of Int. Test. Conf., 1999, pp.77-84 https://doi.org/10.1109/TEST.1999.805616
  5. P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitchm 'A test vector inhibiting technique for low energy BIST design,' Proc. of IEEE VLSI Test Symp., 1999, pp.407-412 https://doi.org/10.1109/VTEST.1999.766696
  6. F.Corno, M. Rebaudengo, and M. S. Reorda, 'Low power BIST via nonliear hybrid cellular automata,' Proc. of IEEE VLSI Test Symp., 2000. pp29-34 https://doi.org/10.1109/VTEST.2000.843823
  7. S. Wang and S. K. Gupta, 'ATPG for heat dissipation minimization during scan testing,' Proc. of Design Automation Conf., 1997, pp. 614-619 https://doi.org/10.1109/DAC.1997.597219
  8. R. Sankaralingam, R.R. Oruganti, and N.A Touba, 'Static compaction techniques to control scan vector power dissipation,' Proc. of IEEE VLSI Test Symp., 2000, pp. 35-40 https://doi.org/10.1109/VTEST.2000.843824
  9. K. Chakrabarty, 'Optimal test access architecture for system-on-chip,' ACM Trans. Design Automation Electron. Syst., vol. 6, pp. 26-49, Jan. 2001 https://doi.org/10.1145/371254.371258
  10. K. Chakrabarty, 'Design of system-on-chip test architectures under place-and-route and power constraints,' Proc. of IEEE/ ACM Design Automation Conf., 2000, pp.432-437 https://doi.org/10.1145/337292.337531
  11. Iyengar, V., Chakrabarty, K., Murray, B.T. 'Built-in self testing of seq. circuits using precomputed test sets,' Proc. of VLSI Test Symposium, 1998. pp.418-423 https://doi.org/10.1109/VTEST.1998.670900
  12. Hamzaoglu, I., Patel, J.H. 'Deterministic test pattern generation techniques for sequential circuits,' Computer Aided Design, 2000. ICCAD-2000. pp.538-543 https://doi.org/10.1109/ICCAD.2000.896528
  13. A. Jas, J. Ghosh-Dastidar, and N. A. Touba, 'Scan Vector Compression/Decompression Using Statistical Coding,' In Proceedings IEEE VLSI Test Symposium, pp. 114 - 121, 1999 https://doi.org/10.1109/VTEST.1999.766654
  14. A. Jas and N. Touba, 'Test Vector Decompression Via Cyclical Scan Chains and Its Application to Testing Core Based Designs,' In Proceedings IEEE International Test Conference, pp. 458 - 464, 1998 https://doi.org/10.1109/TEST.1998.743186
  15. A. Chandra and K Chakrabarty, 'System-on-a-Oiip Test Data Compression and Decompression Architectures Based on Golomb Codes,' IEEE Transactions on Computer Aided Design, Vol. 20, pp. 113 - 120, 2001 https://doi.org/10.1109/43.913754
  16. A. Chandra and K Chakrabarty, 'Frequency-Directed Run-Length (FDR) Codes with Application to System on a Chip Test Data Compression,' In Proceedings IEEE VLSI Test Symposium, pp. 114 - 121, 2001 https://doi.org/10.1109/VTS.2001.923416
  17. Girard, P., 'Survey of Low-power testing of VLSI Circuits,' Design & Test of Computers, IEEE Transactions on, Vol. 19 Issue. 3, 2002, pp.80-90 https://doi.org/10.1109/MDT.2002.1003802
  18. Klaus Holtz and Eric Holtz, 'Lossless Data Compression Techniques,' Proc. of Idea/ Microelectronics, 1994, pp.392-397
  19. B. Pouya and A. Crouch, 'Optimization Trade-offs for Vector Volume and Test Power,' Proc. of Int'l Test Conf.(IYC 00), IEEE Press, Piscata-way, N.J., 2000, pp.873-881 https://doi.org/10.1109/TEST.2000.894298
  20. Wolff F.G., Papachristou C., 'Multiscan-based test compression and hardware decompression using LZ77,' Proc. of Int. Test Conference, 2002. pp.331-339 https://doi.org/10.1109/TEST.2002.1041776
  21. P. Y. Gonciari, B. M AI-Hashimi, and N. Nicolici, 'Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression,' In Proceedings Design, Automation and Test in Europe Conference and Exhibition, pp. 604 - 611, 2002 https://doi.org/10.1109/DATE.2002.998363
  22. Chandra, A., Chakrabarty, K, 'Low-power scan testing and test data compression for system-on-a-chip,' Computer-Aided Design of Integrated Circuits and Systema, IEEE Transactions on, Volume: 21, Issue: 5, May 2002 pp.597-604 https://doi.org/10.1109/43.998630