1 |
M. S. Abadir, M. A. Breuer, 'A Knowledge Based System for Designing Testable VLSI Chips', IEEE Design & Test of Computers, Vol. 2, No. 4, pp. 56-68, August 1985
DOI
ScienceOn
|
2 |
Williams, M. J. Y., and J. B. Angell, 'Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic', IEEE Trans. Comput., Vol. C-22, No. 1, pp. 46-60, January 1973
DOI
|
3 |
Carter, W. C., et al., 'Design of Serviceability Features for the IBM system/360', IBM J. Res. Dev., Vol. 8, pp. 115-126, April 1964
DOI
|
4 |
Alexander Miczo, 'Digital Logic Testing and Simulation', John Wiley & Sons, 1986
|
5 |
'TetraMAX ATPG User Guide', Version 2000-11,Synopsys Inc., 2000
|
6 |
'TetraMAX Release Note', Version 2000-11, Synopsys Inc., 2000
|
7 |
'SynTest User's Guide chapter 6 (Using Pyramid-Test Logic Synthesis and Verification Tools)', SynTest, pp. 31-32, 1998
|
8 |
Pran Kurup and Taher Abbasi, 'Logic Synthesis Using SYNOPSYS 2nd', Kluwer academic publishers, Massachusettes, 1997
|
9 |
M. Abramovici, M. A. Breuer and D. Friedman, 'Digital Systems Testing and Testable Design', Computer Science Press, 1990
|
10 |
'Synopsys manual-Synopsys DFT Compiler Scan Synthesis User Guide chapter 9', Synopsys, pp. 8-11, 2000
|