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A new efficient algorithm for test pattern compression considering low power test in SoC  

신용승 (LG전자 System IC 사업담당)
강성호 (연세대학교 전기전자공학과)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.41, no.9, 2004 , pp. 85-95 More about this Journal
Abstract
As the design complexity increases, it is a major problem that the size of test pattern is large and power consumption is high in scan, especially system-on-a-chip(SoC), with the automatic test equipment(ATE). Because static compaction of test patterns heads to higher power for testing, it is very hard to reduce the test pattern volume for low power testing. This paper proposes an efficient compression/decompression algorithm based on run-length coding for reducing the amount of test data for low power testing that must be stored on a tester and be transferred to SoC. The experimental results show that the new algorithm is very efficient by reducing the memory space for test patterns and the hardware overhead for the decoder.
Keywords
Test pattern compression; Low power test; Run-length code;
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1 B. Pouya and A. Crouch, 'Optimization Trade-offs for Vector Volume and Test Power,' Proc. of Int'l Test Conf.(IYC 00), IEEE Press, Piscata-way, N.J., 2000, pp.873-881   DOI
2 Wolff F.G., Papachristou C., 'Multiscan-based test compression and hardware decompression using LZ77,' Proc. of Int. Test Conference, 2002. pp.331-339   DOI
3 A. Chandra and K Chakrabarty, 'System-on-a-Oiip Test Data Compression and Decompression Architectures Based on Golomb Codes,' IEEE Transactions on Computer Aided Design, Vol. 20, pp. 113 - 120, 2001   DOI   ScienceOn
4 A. Chandra and K Chakrabarty, 'Frequency-Directed Run-Length (FDR) Codes with Application to System on a Chip Test Data Compression,' In Proceedings IEEE VLSI Test Symposium, pp. 114 - 121, 2001   DOI
5 A. Jas and N. Touba, 'Test Vector Decompression Via Cyclical Scan Chains and Its Application to Testing Core Based Designs,' In Proceedings IEEE International Test Conference, pp. 458 - 464, 1998   DOI
6 K. Chakrabarty, 'Design of system-on-chip test architectures under place-and-route and power constraints,' Proc. of IEEE/ ACM Design Automation Conf., 2000, pp.432-437   DOI
7 Iyengar, V., Chakrabarty, K., Murray, B.T. 'Built-in self testing of seq. circuits using precomputed test sets,' Proc. of VLSI Test Symposium, 1998. pp.418-423   DOI
8 Hamzaoglu, I., Patel, J.H. 'Deterministic test pattern generation techniques for sequential circuits,' Computer Aided Design, 2000. ICCAD-2000. pp.538-543   DOI
9 P. Y. Gonciari, B. M AI-Hashimi, and N. Nicolici, 'Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression,' In Proceedings Design, Automation and Test in Europe Conference and Exhibition, pp. 604 - 611, 2002   DOI
10 Chandra, A., Chakrabarty, K, 'Low-power scan testing and test data compression for system-on-a-chip,' Computer-Aided Design of Integrated Circuits and Systema, IEEE Transactions on, Volume: 21, Issue: 5, May 2002 pp.597-604   DOI   ScienceOn
11 Girard, P., 'Survey of Low-power testing of VLSI Circuits,' Design & Test of Computers, IEEE Transactions on, Vol. 19 Issue. 3, 2002, pp.80-90   DOI   ScienceOn
12 Klaus Holtz and Eric Holtz, 'Lossless Data Compression Techniques,' Proc. of Idea/ Microelectronics, 1994, pp.392-397
13 K. Chakrabarty, 'Optimal test access architecture for system-on-chip,' ACM Trans. Design Automation Electron. Syst., vol. 6, pp. 26-49, Jan. 2001   DOI   ScienceOn
14 A. Jas, J. Ghosh-Dastidar, and N. A. Touba, 'Scan Vector Compression/Decompression Using Statistical Coding,' In Proceedings IEEE VLSI Test Symposium, pp. 114 - 121, 1999   DOI
15 S. Wang and S. K. Gupta, 'ATPG for heat dissipation minimization during scan testing,' Proc. of Design Automation Conf., 1997, pp. 614-619   DOI
16 R. Sankaralingam, R.R. Oruganti, and N.A Touba, 'Static compaction techniques to control scan vector power dissipation,' Proc. of IEEE VLSI Test Symp., 2000, pp. 35-40   DOI
17 R.M. Chou, K. K. Saluja, and V.D. Agrawal, 'Scheduling test for VLSI systems under power constraints,' IEEE Trans. VLSI Syst., vol 5, pp.175-l85, June 1997   DOI   ScienceOn
18 S.Wang and S.K. Gupta, 'LT-RTPG: A new test-per-scan BIST TPG for low heat disspation,' Proc. of Int. Test. Conf., 1990, pp. 84-94   DOI
19 S.Gerstendorfer and H.J. Wunderlich, 'Minimized power consumption for scan-based BIST,' Proc. of Int. Test. Conf., 1999, pp.77-84   DOI
20 P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitchm 'A test vector inhibiting technique for low energy BIST design,' Proc. of IEEE VLSI Test Symp., 1999, pp.407-412   DOI
21 F.Corno, M. Rebaudengo, and M. S. Reorda, 'Low power BIST via nonliear hybrid cellular automata,' Proc. of IEEE VLSI Test Symp., 2000. pp29-34   DOI
22 Y. Zorian, 'A distributed BIST control scheme for complex VLSI devices,' Proc. of IEEE VLSI Test Symp., 1993, pp4-9   DOI