The Transactions of the Korean Institute of Electrical Engineers D (대한전기학회논문지:시스템및제어부문D)

The Korean Institute of Electrical Engineers (대한전기학회)
권호 표지

A Low Power scan Design Architecture

저전력을 고려한 스캔 체인 구조 변경

  • 민형복 (성균관대학교 정보통신공학부) ;
  • 김인수 (성균관대학교 전기전자 및 컴퓨터 공학과)
  • Published : 2005.07.01
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Abstract

Power dissipated during test application is substantially higher than power dissipated during functional operation which can decrease the reliability and lead to yield loss. This paper presents a new technique for power minimization during test application in full scan sequential circuits. This paper shows freezing of combinational logic parts during scan shift operation in test mode. The freezing technique leads to power to minimization. Significant power reduction in the scan techniques is achieved on ISCAS 89 benchmarks.

Keywords

References

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