• Transactions on Electrical and Electronic Materials
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• v.12 no.1
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• pp.7-10
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• 2011

High voltage (HV) integrated circuits are viable alternatives to discrete circuits in a wide variety of applications. A HV device generally used in these circuits is a lateral double diffused metal oxide semiconductor (LDMOS) transistor. Attempts to model LDMOS devices are complicated by the existence of the lightly doped drain and by the extension of the poly-silicon and the gate oxide. Several physically based investigations of the bias-dependent drift resistance of HV devices have been conducted, but a complete physical model has not been reported. We propose a new technique to model HV devices using both the BSIM3 SPICE model and a bias dependent resistor model (sub-circuit macro model).

• Journal of Korean Neurosurgical Society
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• v.59 no.3
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• pp.322-324
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• 2016

To introduce a new device for catheter placement of an external ventricular drain (EVD) of cerebrospinal fluid (CSF). This device was composed of three portions, T-shaped main body, rectangular pillar having a central hole to insert a catheter and an arm pointing the tragus. The main body has a role to direct a ventricular catheter toward the right or left inner canthus and has a shallow longitudinal opening to connect the rectangular pillar. The arm pointing the tragus is controlled by back and forth movement and turn of the pillar attached to the main body. Between April 2012 and December 2014, 57 emergency EVDs were performed in 52 patients using this device in the operating room. Catheter tip located in the frontal horn in 52 (91.2%), 3rd ventricle in 2 (3.5%) and in the wall of the frontal horn of the lateral ventricle in 3 EVDs (5.2%). Small hemorrhage along to catheter tract occurred in 1 EVD. CSF was well drained through the all EVD catheters. The accuracy of the catheter position and direction using this device were 91% and 100%, respectively. This device for EVD guides to provide an accurate position of catheter tip safely and easily.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.585-593
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• 2015

In the nanoscale regime, many multigate devices are explored to reduce their size further and to enhance their performance. In this paper, design of a novel device called, Triple Material Surrounding Gate Tunnel Field effect transistor (TMSGTFET) has been developed and proposed. The advantages of surrounding gate and tunnel FET are combined to form a new structure. The gate material surrounding the device is replaced by three gate materials of different work functions in order to curb the short channel effects. A 2-D analytical modeling of the surface potential, lateral electric field, vertical electric field and drain current of the device is done, and the results are discussed. A step up potential profile is obtained which screens the drain potential, thus reducing the drain control over the channel. This results in appreciable diminishing of short channel effects and hot carrier effects. The proposed model also shows improved ON current. The excellent device characteristics predicted by the model are validated using TCAD simulation, thus ensuring the accuracy of our model.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.3
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• pp.173-181
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• 2005

A new two dimensional (2-D) model for the potential distribution of fully depleted short-channel ion-implanted silicon MESFET's has been presented in this paper. The solution of the 2-D Poisson's equation has been considered as the superposition of the solutions of 1-D Poisson's equation in the lateral direction and the 2-D homogeneous Laplace equation with suitable boundary conditions. The minimum bottom potential at the interface of the depletion region due to the metal-semiconductor junction at the Schottky gate and depletion region due to the substrate-channel junction has been used to investigate the drain-induced barrier lowering (DIBL) and its effects on the threshold voltage of the device. Numerical results have been presented for the potential distribution and threshold voltage for different parameters such as the channel length, drain-source voltage, and implanted-dose and silicon film thickness.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.1
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• pp.109-114
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• 2002

In this paper, we have presented the simulation results ah)ut threshold voltage for Si-based MOSFETs with channel length of nano scale. We simulated the Si-based n channel MOSFETs with gate lengths from 180 to 30 nm in accordance to the constant voltage scaling theory and the lateral scaling. These MOSFETs had the lightly doped drain(LDD) structure, which is used for the reduction of electric field magnitude and short channel effects at the drain region. The stronger electric field at this region is due to scaling down. We investigated and analyzed the threshold voltage of these devices. This analysis will provide insight into some applicable limitations at the ICs and used for basis data at VLSI.

• Journal of the Korean Vacuum Society
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• v.1 no.1
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• pp.212-222
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• 1992

To use polycrystalline Si Thin Film Transistor (poly-Si TFT) in high density SRAM instead of High Load Resistor (HLR), TFT is needed to show good electrical characteristics such as large carrier mobility, low leakage current, high driver current and low subthreshold swing. To satisfy these electrical characteristics, the trap state density must be reduced in the channel poly. Technological issues pertinent to the channel poly fabrication process are investigated and discussed. They are solid phase growth (SPG), Si-ion implantation, laser annealing and hydrogenation. The electrical properties of several CVD oxides used as the gate oxide of TFT are compared. The dependence of the electrical characteristics of TFT on source-drain ion-implantation dose, drain offset length and dopant lateral diffusion are also described.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.10
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• pp.489-493
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• 2001

The on-current of offset and LDD structured devices in slightly decreased while the off-current are remarkably reduced and almost constant independent of gate and drain voltage because offset and LDD regions behave as a series resistance and reduce the lateral electric field in the drain depletion. Degradation of these devices is dependent upon the offset and LDD length rather than doping concentration in these regions. Also, degradation mechanism has been related to the interface generation rather than the hot carrier injection into gate oxide.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.26-29
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• 1999

The I-V characteristics of the n-channel offset gated poly-Si TETs have been systematically investigated in order to analyse the effects of offset region. The on currents are reduced due to the series resistance by the offset length and there is no kink phenomenon in offset devices. The off currents of the offset gated TFTs are remarkably reduced to 10$^{-12}$ A independent of gate and drain voltage because the electric field is weakened by the increase of the depletion region width near the drain region. It is shown that the offset regions behave as a series resistance and reduce lateral and vertical electric field.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.111-120
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• 2011

A two-dimensional analytical model for deriving the threshold voltage of a short channel fully depleted (FD) cylindrical/surrounding gate MOSFET (CGT/SGT) is suggested. By taking into account the lateral variation of the surface potential, introducing the natural length expression, and using the Bessel functions of the first and the second kinds of order zero, we can derive potentials in the gate oxide layer and the silicon core fully two-dimensionally. Making use of these potentials, the minimum surface potential can be obtained to derive the threshold voltage as a closed-form expression in terms of various device parameters and applied voltages. Obtained results can be used to explain the drain-induced threshold voltage roll-off of a CGT/SGT in a unified manner.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.140-140
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• 2010

Non-mass analyzed ion shower doping (ISD) technique with a bucket-type ion source or mass-analyzed ion implantation with a ribbon beam-type has been used for source/drain doping, for LDD (lightly-doped-drain) formation, and for channel doping in fabrication of low-temperature poly-Si thin-film transistors (LTPS-TFT's). We reported an abnormal activation behavior in boron doped poly-Si where reverse annealing, the loss of electrically active boron concentration, was found in the temperature ranges between $400^{\circ}C$ and $650^{\circ}C$ using isochronal furnace annealing. We also reported reverse annealing behavior of sequential lateral solidification (SLS) poly-Si using isothermal rapid thermal annealing (RTA). We report here the importance of implantation conditions on the dopant activation. Through-doping conditions with higher energies and doses were intentionally chosen to understand reverse annealing behavior. We observed that the implantation condition plays a critical role on dopant activation. We found a certain implantation condition with which the sheet resistance is not changed at all upon activation annealing.