• Transactions on Electrical and Electronic Materials
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• 제15권2호
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• pp.87-90
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• 2014

The effects of electric field frequency on the ac electrical treeing phenomena in an epoxy/reactive diluent/layered silicate (1.5 wt%) were carried out, in needle-plate electrode arrangement. A layered silicate was exfoliated in an epoxy base resin, by using our ac electric field apparatus. To measure the treeing propagation rate, constant alternating current (AC) of 10 kV with three different electric field frequencies (60, 500 and 1,000 Hz) was applied to the specimen, in needle-plate electrode arrangement, at $30^{\circ}C$ of insulating oil bath. As the electric field frequency increased, the treeing propagation rate increased. At 500 Hz, the treeing propagation rate of the epoxy/PG/nanosilicate system was $0.41{\times}10^{-3}$ mm/min, which was 3.4 times slower than that of the epoxy/PG system. The electrical treeing morphology was dense bush type at 60 Hz; however, as the frequency increased, the bush type was changed to branch type, having few branches, with very slow propagation rate.

• 한국세라믹학회:학술대회논문집
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• 한국세라믹학회 2003년도 춘계총회 및 연구발표회 초록집
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• pp.177.2-177
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• 2003

• 전자공학회논문지
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• 제50권4호
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• pp.239-245
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• 2013

멀티 레벨 낸드 플레쉬 메모리에서 주위 셀의 문턱 전압상태에 따른 데이터 유지 특성을 연구하였다. 열을 가해 셀의 데이터 보전특성을 판정하는 열적 열하 특성에서 주목하는 셀의 문턱 전압이 변화하는데 문턱전압의 변화는 선택된 셀 주위에 있는 셀들이 가장 낮은 문턱 전압 상태로 있는 셀들의 수가 많을수록 커진다. 그 이유는 전하의 손실이 이루어지는 낸드 플레쉬 셀의 본질적인 특성 뿐 아니라, 주위 셀 사이의 측면 전계 때문이다. 전계에 대한 모사 결과로부터 전계의 증가 현상을 발견할 수 있고, 이로 인한 전하의 손실이 소자 스케일 다운에 따라 더 증가함을 알 수 있다.

• Advances in nano research
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• 제1권4호
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• pp.203-210
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• 2013

So far, all reviews and control approaches of spin relaxation have been done on lateral single electron quantum dots. In such structures, many efforts have been done, in order to eliminate spin-lattice relaxation, to obtain equal Rashba and linear Dresselhaus parameters. But, ratio of these parameters can be adjustable up to 0.7 in a material like GaAs under high-electric field magnitudes. In this article we have proposed a single electron QD structure, where confinements in all of three directions are considered to be almost identical. In this case the effect of cubic Dresselhaus interaction will have a significant amount, which undermines the linear effect of Dresselhaus while it was destructive in lateral QDs. Then it enhances the ratio of the Rashba and Dresselhaus parameters in the proposed structure as much as required and decreases the spin states up and down mixing and the deviation angle from the net spin-down As a result to the least possible value.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 정기총회 및 추계학술대회 논문집 학회본부
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• pp.243-245
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• 1993

The negative curvature effect on the breakdown voltage of p-n junction, which may realize 1-D breakdown voltage due to the lower peak electric field at the junction, is proposed and verified by the fabrication of lateral diode on Silicon-on-Insulator (SOI) together with MEDICI simulation. The experimental and simulation results show good agreements with the theoretical expectation. The proposed method is effectively applicable to the lateral, especially on SOI, power devices.

• ETRI Journal
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• 제39권2호
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• pp.284-291
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• 2017

Drain-induced barrier lowering (DIBL) is one of the main parameters employed to indicate the short-channel effect for nano metal-oxide semiconductor field-effect transistors (MOSFETs). We propose a new physical model of the DIBL effect under two-dimensional approximations based on the energy-conservation equation for channel electrons in FETs, which is different from the former field-penetration model. The DIBL is caused by lowering of the effective potential barrier height seen by the channel electrons because a lateral channel electric field results in an increase in the average kinetic energy of the channel electrons. The channel length, temperature, and doping concentration-dependent DIBL effects predicted by the proposed physical model agree well with the experimental data and simulation results reported in Nature and other journals.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 D
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• pp.1337-1339
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• 1998

The trench termination scheme is introduced for high voltage devices. The curvature of the depletion region at field limiting ring is critical factor to determine the breakdown voltage. The smooth curvature of the depletion junction alleviate the electric field crowding effect around this region. In the trench field limiting ring, the radius of the depletion region is smaller than conventional field limiting ring, but the distance between every trench is spaced small enough to punchthrough before initiation of local breakdown. The trench field limiting ring on silicon can ne formed by RIE followed by oxidation on side wall surface of the trench, and polysilicon filling. The combined termination of this trench floating field ring and field plate have been designed and analyzed. The breakdown simulation by 2-dimensional TCAD shows that the cylindrical junction breakdown voltage for substrate doping might be 99 percent of the ideal breakdwon voltage for substrate doping concentration of $3\times10^{14}cm^{-3}$ with about $100{\mu}m$ of lateral termination width.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권6호
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• pp.585-593
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• 2015

In the nanoscale regime, many multigate devices are explored to reduce their size further and to enhance their performance. In this paper, design of a novel device called, Triple Material Surrounding Gate Tunnel Field effect transistor (TMSGTFET) has been developed and proposed. The advantages of surrounding gate and tunnel FET are combined to form a new structure. The gate material surrounding the device is replaced by three gate materials of different work functions in order to curb the short channel effects. A 2-D analytical modeling of the surface potential, lateral electric field, vertical electric field and drain current of the device is done, and the results are discussed. A step up potential profile is obtained which screens the drain potential, thus reducing the drain control over the channel. This results in appreciable diminishing of short channel effects and hot carrier effects. The proposed model also shows improved ON current. The excellent device characteristics predicted by the model are validated using TCAD simulation, thus ensuring the accuracy of our model.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.342-343
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• 2012

We studied the Drain-Induced-Barrier-Lowering (DIBL) effect by different drain engineering. One other drain engineering is symmetric source-drain n-channel MOSFETs (SSD NMOSs), the other drain engineering is asymmetric source-drain n-channel MOSFETs (ASD NMOSs). Devices were fabricated using state of art 40 nm dynamic-random-access-memory (DRAM) technology. These devices have different modes which are deep drain junction mode in SSD NMOSs and shallow drain junction mode in ASD NMOSs. The shallow drain junction mode means that drain is only Lightly-Doped-Drain (LDD). The deep drain junction mode means that drain have same process with source. The threshold voltage gap between low drain voltage ($V_D$=0.05V) and high drain voltage ($V_D$=3V) is 0.088V in shallow drain junction mode and 0.615V in deep drain junction mode at $0.16{\mu}m$ of gate length. The DIBL coefficients are 26.5 mV/V in shallow drain junction mode and 205.7 mV/V in deep drain junction mode. These experimental results present that DIBL effect is higher in deep drain junction mode than shallow drain junction mode. These results are caused that ASD NMOSs have low drain doping level and low lateral electric field.

• 한국전기전자재료학회논문지
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• 제35권1호
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• pp.18-23
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• 2022

이젯 프린팅은 직접적인 비접촉 마이크로 팹기술의 하나로서 노즐과 기판 사이에 강한 전기장을 가함으로써 넓은 범위의 마이크로/나노패턴 어레이를 구현할 수 있는 다목적 팹공정이다. 제조된 고분자/퀀텀닷 마이이크로 패턴의 모양과 두께는 자동화된 프린트 기계에 설치된 노즐 직경과 공정에 사용된 잉크 성분에 일반적으로 정밀한 의존성을 갖는다. 본 논문의 목적은 실험 결과에 영향을 미칠 수 있는 각각의 공정 변수 효과를 설명하기 위해서 이젯 프린팅된 고분자/퀀텀닷의 전형적인 실제 예를 설명하는데 있다. 여기서 우리는 마이크로/나노 해상도로 두께가 정밀하게 제어된 고분자/퀀텀닷 패턴을 제조할 수 있는 몇 가지 이젯 프린팅 공정을 구현하였다.