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http://dx.doi.org/10.5573/ieek.2013.50.4.239

Study of Data Retention Characteristics with surrounding cell's state in a MLC NAND Flash Memory  

Choi, Deuk-Sung (Dept. of Electronic & Information Engineering, YNC)
Choi, Sung-Un (Dept. of Electronic & Information Engineering, YNC)
Park, Sung-Kye (Memory R&D Divison, SK Hynix)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.50, no.4, 2013 , pp. 239-245 More about this Journal
Abstract
The data retention characteristics depending on neighbor cell's threshold voltage (Vt) in a multilevel NAND flash memory is studied. It is found that a Vt shift (${\Delta}Vt$) of the noted cell during a thermal retention test is increased as the number of erase-state (lowest Vt state) cells surrounding the noted cell increases. It is because a charge loss from a floating gate is originated from not only intrinsic mechanism but also lateral electric field between the neighboring cells. From the electric field simulation, we can find that the electric field is increased and it results in the increased charge loss as the device is scaled down.
Keywords
Multi-level Cell NAND Flash (MLC NAND FLASH); Retention Characteristics; Bake Test; Neighboring Cell State; Lateral Electric Field Effect;
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