• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.8
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• pp.3201-3223
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• 2020

Wireless communication has become the promising technology in the recent times because of its applications in Internet of Things( IoT) devices. The IEEE 802.15.4e has become the key technology for IoT devices which utilizes the Time-Slotted Channel Hopping (TSCH) networks for the communication between the devices. In this paper, we develop a Two Level Scheduling Algorithm (TLSA) for scheduling multiple packets with different arrival rate at the source nodes in a TSCH networks based on the link activated by a centralized scheduler. TLSA is developed by considering three types of links in a network such as link i with packets arrival type 1, link j with packets arrival type 2, link k with packets arrival type 3. For the data packets arrival, two stages in a network is considered.At the first stage, the packets are considered to be of higher priority.At the second stage, the packets are considered to be of lower priority.We introduce level 1 schedule for the packets at stage 1 and level 2 schedule for the packets at stage 2 respectively. Finally, the TLSA is validated with the two different energy functions i.e., y = e^ax - 1 and y = 0.5x² using MATLAB 2017a software for the computation of average and worst ratios of the two levels.

• Journal of Korean Institute of Industrial Engineers
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• v.40 no.3
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• pp.283-290
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• 2014

In the flat panel display industry, to meet production target quantities and the deadline of production, the scheduler and dispatching systems are major production management systems which control the order of facility production and the distribution of WIP (Work In Process). Especially the delivery time is a key factor of the dispatching system for the time when a lot can be supplied to the facility. In this paper, we use survival analysis methods to identify main factors of the delivery time and to build the delivery time forecasting model. To select important explanatory variables, the cox proportional hazard model is used to. To make a prediction model, the accelerated failure time (AFT) model was used. Performance comparisons were conducted with two other models, which are the technical statistics model based on transfer history and the linear regression model using same explanatory variables with AFT model. As a result, the mean square error (MSE) criteria, the AFT model decreased by 33.8% compared to the statistics prediction model, decreased by 5.3% compared to the linear regression model. This survival analysis approach is applicable to implementing the delivery time estimator in display manufacturing. And it can contribute to improve the productivity and reliability of production management system.

• Journal of Sensor Science and Technology
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• v.24 no.2
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• pp.124-130
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• 2015

This paper presents a high performance HIGHT processor that can be applicable for CCM mode. In fact, HIGHT algorithm is a 64-bit block cipher. However, the proposed HIGHT extends the basic block length to 128-bit. The proposed HIGHT is operated as 128-bit block cipher and it can treat 128-bit block at once. Thus, it can be applicable for the various WSN applications that need fast and ultralight 128-bit block cipher, in particular, to be operated in CCM mode. In addition, the proposed HIGHT processor shares the common logics such as 128-bit key scheduler and control logics during encryption and decryption to reduce the area overhead caused by the extension of data block length. From the simulation results, the circuit area and power consumption of the proposed HIGHT are increases as 40% and 64% compared to the conventional 64-bit counterpart. However, the throughput of the proposed HIGHT can be up to two times as fast. Consequently, the proposed HIGHT is useful for USN and handheld devices based on battery as well as RFID tag the size of circuit is less than 5,000 gates.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.53-64
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm, "Rijndael". An iterative looping architecture using a single round block is adopted to minimize the hardware required. To achieve high throughput rate, a sub-pipeline stage is added by dividing the round function into two blocks, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. The round block is implemented using 32-bit data path, so each sub-pipeline stage is executed for four clock cycles. The S-box, which is the dominant element of the round block in terms of required hardware resources, is designed using arithmetic circuit computing multiplicative inverse in GF($2^8$) rather than look-up table method, so that encryption and decryption can share the S-boxes. The round keys are generated by on-the-fly key scheduler. The crypto-processor designed in Verilog-HDL and synthesized using 0.25-$\mu\textrm{m}$ CMOS cell library consists of about 23,000 gates. Simulation results show that the critical path delay is about 8-ns and it can operate up to 120-MHz clock Sequency at 2.5-V supply. The designed core was verified using Xilinx FPGA board and test system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.11
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• pp.2093-2099
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• 2016

This paper describes a design of crypto-processor that supports multiple block cipher algorithms of PRESENT, ARIA, and AES. The crypto-processor integrates three cores that are PRmo (PRESENT with mode of operation), AR_AS (ARIA_AES), and AES-16b. The PRmo core implementing 64-bit block cipher PRESENT supports key length 80-bit and 128-bit, and four modes of operation including ECB, CBC, OFB, and CTR. The AR_AS core supporting key length 128-bit and 256-bit integrates two 128-bit block ciphers ARIA and AES into a single data-path by utilizing resource sharing technique. The AES-16b core supporting key length 128-bit implements AES with a reduced data-path of 16-bit for minimizing hardware. Each crypto-core contains its own on-the-fly key scheduler, and consecutive blocks of plaintext/ciphertext can be processed without reloading key. The crypto-processor was verified by FPGA implementation. The crypto-processor implemented with a $0.18{\mu}m$ CMOS cell library occupies 54,500 gate equivalents (GEs), and it can operate with 55 MHz clock frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.9
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• pp.1993-1999
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• 2011

This paper describes a design of area-efficient/low-power cryptographic processor for HIGHT block cipher algorithm, which was approved as standard of cryptographic algorithm by KATS(Korean Agency for Technology and Standards) and ISO/IEC. The HIGHT algorithm, which is suitable for ubiquitous computing devices such as a sensor in USN or a RFID tag, encrypts a 64-bit data block with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we optimize round transform block and key scheduler to share hardware resources for encryption and decryption. The HIGHT64 core synthesized using a 0.35-${\mu}m$ CMOS cell library consists of 3,226 gates, and the estimated throughput is 150-Mbps with 80-MHz@2.5-V clock.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.67-74
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• 2008

A compact and high-performance AES(Advanced Encryption Standard) encryption/decryption processor is designed by applying various hardware sharing and optimization techniques. In order to achieve minimized hardware complexity, sharing the S-Boxes for round transformation with the key scheduler, as well as merging and reusing datapaths for encryption and decryption are utilized, thus the area of S-Boxes is reduced by 25%. Also, the S-Boxes which require the largest hardware in AES processor is designed by applying composite field arithmetic on $GF(((2^2)^2)^2)$, thus it further reduces the area of S-Boxes when compared to the design based on $GF(2^8)$ or $GF((2^4)^2)$. By optimizing the operation of the 64-bit round transformation and round key scheduling, the round transformation is processed in 3 clock cycles and an encryption of 128-bit data block is performed in 31 clock cycles. The designed AES processor has about 15,870 gates, and the estimated throughput is 412.9 Mbps at 100 MHz clock frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.125-128
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• 2011

This paper describes an efficient hardware implementation of HIGHT block cipher algorithm, which was approved as standard of cryptographic algorithm by KATS(Korean Agency for Technology and Standards) and ISO/IEC. The HIGHT algorithm, which is suitable for ubiquitous computing devices such as a sensor in USN or a RFID tag, encrypts a 64-bit data block with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we optimize round transform block and key scheduler to share hardware resources for encryption and decryption. The HIGHT64 core synthesized using a $0.35-{\mu}m$ CMOS cell library consists of 3,226 gates, and the estimated throughput is 150-Mbps with 80-MHz@2.5-V clock.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.12
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• pp.67-74
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• 2004

AES is frequently used as a symmetric cryptography algorithm for the Internet. Wireless embedded systems increasingly use more conventional wired network protocols. Hence, it is important to have low-cost implementations of AES for thor The basic architecture of AES unrolls oかy one full cipher round which uses 20 S-boxes together with the key scheduler and the algorithm repeatedly executes it. To reduce the implementation cost further, the folded architecture which uses only eight S-box units was studied in the recent years. In this paper, we will study a low-cost AES implementation for wireless communication technology based on the folded architecture. We first improve the folded architecture to avoid the sixteen bytes of additional state memory. Then, we implemented a single byte architecture where only one S-box unit is used for data encryption and key scheduling. It takes 352 clocks to finish a complete encryption. We found that the maximum clock frequency of its FPGA implementation reaches about 40 MHz. It can achieve about 13 Mbps which is enough for 3G wireless communication technology.

• Journal of Korea Multimedia Society
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• v.4 no.5
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• pp.371-376
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• 2001

Since continuous media such as video and audio data are displayed within a certain time constraint, their computation and manipulation should be handled under limited condition. Traditional real-time scheduling algorithms cold be directly applicable, because they are not suitable for multimedia scheduling applications which support many clients at the same time. Rate Regulating Proportional Share Scheduling Algorithm based on the stride scheduler is a scheduling algorithm considered the time constraint of the continuous media. The stride schedulers, which are designed to general tasks, guarantee the fairness of resource allocation and predictability. The key concept of RRPSSA is a rate regulator which prevents tasks from receiving more resource than its share in a given period. But this algorithm loses fairness which is a strong point of the stride schedulers, and does not show graceful degradation of performance under overloaded situation. This paper proposes a new modified algorithm, namely Modified Proportional Share Scheduling Algorithm considering the characteristics of multimedia data such as its continuity and time dependency. Proposed scheduling algorithm shows graceful degradation of performance in overloaded situation and it reduces the scheduling violations up to 70% by maintaining the fair resource allocation. The number of context switching is 8% less than RRPSSA and the overall performance is increased.