An Efficient Hardware Implementation of AES Rijndael Block Cipher Algorithm
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안하기
(금오공과대학교 전자공학부 VLSI 설계연구실)
신경욱 (금오공과대학교 전자공학부) |
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Improved VLSI designs for multiplication and inversion in GF(2m) over normal bases
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Rijndael 암호 알고리즘을 구현한 암호 프로세서의 설계
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과학기술학회마을 |
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Systolic array implementation of Euclid's algorithm for inversion and division in GF(2m)
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Announcing the Advanded Encryption Standard(AES)
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Architectural optimization for a 1.82Gbits/sec VLSI implementation of the AES Rijndael Algorithm
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VLSI architecture for computing exponentiations, multiplicative inverses, and divisions
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DOI ScienceOn |
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Data Encryption Standard
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AES Proposal : Rijndael Block Cipher
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A method for obtaining digital signatures and public-key cryptosystems
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DOI ScienceOn |
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Highspeed easily testable Galois-field inverter
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DOI ScienceOn |
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An FPGA-based Performance evaluation of the AES block cipher candidate algorithm finalists
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Elliptic Curves in Cryptography
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GF(2m) multiplication and division over the dual basis
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DOI ScienceOn |
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A VLSI architecture for fast inversion in GF(2m)
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An embedded Cryptographic processor for the Rijndael AES algorithm
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A low latency architecture for computing multiplicative inverses and divisions in GF(2m)
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