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Low-Cost AES Implementation for Wireless Embedded Systems  

LEE Dong-Ho (School of Electrical Engineering and Computer Science, Kyungpook National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.41, no.12, 2004 , pp. 67-74 More about this Journal
Abstract
AES is frequently used as a symmetric cryptography algorithm for the Internet. Wireless embedded systems increasingly use more conventional wired network protocols. Hence, it is important to have low-cost implementations of AES for thor The basic architecture of AES unrolls oかy one full cipher round which uses 20 S-boxes together with the key scheduler and the algorithm repeatedly executes it. To reduce the implementation cost further, the folded architecture which uses only eight S-box units was studied in the recent years. In this paper, we will study a low-cost AES implementation for wireless communication technology based on the folded architecture. We first improve the folded architecture to avoid the sixteen bytes of additional state memory. Then, we implemented a single byte architecture where only one S-box unit is used for data encryption and key scheduling. It takes 352 clocks to finish a complete encryption. We found that the maximum clock frequency of its FPGA implementation reaches about 40 MHz. It can achieve about 13 Mbps which is enough for 3G wireless communication technology.
Keywords
Cryptography; Computer Architecture; Wireless Communication; Security;
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