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http://dx.doi.org/10.6109/jkiice.2011.15.9.1993

An efficient hardware implementation of 64-bit block cipher algorithm HIGHT  

Park, Hae-Won (금오공과대학교 전자공학부)
Shin, Kyung-Wook (금오공과대학교 전자공학부)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.15, no.9, 2011 , pp. 1993-1999 More about this Journal
Abstract
This paper describes a design of area-efficient/low-power cryptographic processor for HIGHT block cipher algorithm, which was approved as standard of cryptographic algorithm by KATS(Korean Agency for Technology and Standards) and ISO/IEC. The HIGHT algorithm, which is suitable for ubiquitous computing devices such as a sensor in USN or a RFID tag, encrypts a 64-bit data block with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we optimize round transform block and key scheduler to share hardware resources for encryption and decryption. The HIGHT64 core synthesized using a 0.35-${\mu}m$ CMOS cell library consists of 3,226 gates, and the estimated throughput is 150-Mbps with 80-MHz@2.5-V clock.
Keywords
HIGHT algorithm; block cipher; cryptographic processor; information security;
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