• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.302-317
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• 2017

This paper proposes a new full adder design based on pass-transistor logic that offers ultra-low power dissipation and superior variability together with low transistor count. The pass-transistor logic allows device count reduction through direct logic realization, and thus leads to reduction in the node capacitances as well as short-circuit currents due to the absence of supply rails. Optimum transistor sizing alleviates the adverse effects of process variations on performance metrics. The design is subjected to a comparative analysis against existing designs based on Monte Carlo simulations in a SPICE environment, using the 22-nm CMOS Predictive Technology Model (PTM). The proposed ULP adder offers 38% improvement in power in comparison to the best performing conventional designs. The trade-off in delay to achieve this power saving is estimated through the power-delay product (PDP), which is found to be competitive to conventional values. It also offers upto 79% improvement in variability in comparison to conventional designs, and provides suitable scalability in supply voltage to meet future demands of energy-efficiency in portable applications.

• ETRI Journal
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• 제36권2호
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• pp.321-324
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• 2014

This letter describes a two-phase clock oxide thin-film transistor shift register that executes a robust operation over a wide threshold voltage range and clock coupling noises. The proposed circuit employs an additional Q generation block to avoid the clock coupling noise effects. A SMART-SPICE simulation shows that the stable shift register operation is established for the clock coupling noises and the threshold voltage variation from -4 V to 5 V at a line time of $5{\mu}s$. The magnitude of coupling noises on the Q(15) node and Qb(15) node of the 15th stage is respectively -12.6 dB and -26.1 dB at 100 kHz in the proposed circuit, compared to 6.8 dB and 10.9 dB in a conventional one. In addition, the estimated power consumption is 1.74 mW for the proposed 16-stage shift registers at $V_{TH}=-1.56V$, compared to 11.5 mW for the conventional circuits.

• Journal of electromagnetic engineering and science
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• 제13권1호
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• pp.54-61
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• 2013

An equivalent model has been developed to estimate the electromagnetic immunity for integrated circuits under a complex electromagnetic environment. The complete model is based on the characteristics of the equipment and physical configuration of the device under test (DUT) and describes the measurement setup as well as the target integrated circuits under test, the corresponding package, and a specially designed printed circuit board. The advantage of the proposed model is that it can be applied to a SPICE-like simulator and the immunity of the integrated circuits can be easily achieved without costly and time-consuming measurements. After simulation, measurements were performed to verify the accuracy of the equivalent model for immunity prediction. The improvement of measurement accuracy due to the added effect of a bi-directional coupler in the test setup is also addressed.

• 대한전자공학회논문지SD
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• 제40권4호
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• pp.13-20
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• 2003

반도체 소자이론에 근거한 집적회로용 BJT의 역포화 전류 모델을 제시한다. 공정 조건으로부터 베이스 영역의 불순물 분포를 구하는 방법과 원형 에미터 구조를 갖는 Lateral PNP BJT와 Vertical NPN BJT의 베이스 Gummel Number를 정교하게 계산하는 방법을 제시한다. 제안된 방법의 타당성을 검증하기 위해 20V와 30V 공정을 기반으로 제작한 NPN BJT와 PNP BJT의 역포화 전류를 실측치와 비교한 결과, NPN BJT는 6.7%의 평균상대오차를 보이고 있으며 PNP BJT는 6.0%의 평균 상태오차를 보인다.

• 패션비즈니스
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• 제10권4호
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• pp.114-129
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• 2006

This purpose of this study is to research on the influence on the creation of young generation's street fashion of pop stars focused on pop music given the fact that fashion can be created by popular culture in this multi-media era. Also, this study is to provide useful data for the activation of the creation of young fashion culture and the fashion industry through pop stars' fashion. The pop stars' fashion that has affected young street fashion is as follows : Elvis Presley's rock'n'roll style, Beatles' mods style, Janis Joplin's hippy style, Sex Pistols's punk style, Madonna's boy-toy and corset style, Michael Jackson's androgynous style, Puff Daddy and L.L Cool J's hip-hop style, Bob Marley's reggae style, Spice Girls, Jennifer Lopez and Britney Spears's sexy style. The young street fashion culture of pop stars and its industrial meaning withdrawn from the above are as follows : Creation of a fashion icon, Creation of anti-fashion, Liberation of a sex role, Costume play culture, Activation of the young fashion industry through star marketing.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.463-470
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• 2014

A Verilog model is proposed for transmission lines to perform the all-Verilog simulation of high-speed chip-to-chip interface system, which reduces the simulation time by around 770 times compared to the mixed-mode simulation. The single-pulse response of transmission line in SPICE model is converted into that in Verilog model by converting the full-scale analog signal into an 11-bit digital code after uniform time sampling. The receiver waveform of transmission line is calculated by adding or subtracting the single-pulse response in Verilog model depending on the transmitting digital code values with appropriate time delay. The application of this work to a USB 2.0 high-speed PHY interface reduces the simulation time to less than three minutes with error less than 5% while the mixed-mode simulation takes more than two days for the same circuit.

• 전자공학회논문지A
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• 제31A권8호
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• pp.46-52
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• 1994

DC and AC current crowding effects for microwave and high speed bipolar transistors are investigated in detail using a new and accurate measurement technique based on Z-parameter equationa. Using the new measurement technique dc and ac current crowding effects have been explained clearly in bipolar junction transistors. To model ac crowding effects a capacitive element defined as base capacitance (C$_b$), called ac crowding capacitance is added to base resistance in parallel thereby treating the base resistance(R$_b$) as base impedance Z$_b$. It is shown that base resistance decreases with increasing collector current due to dc current crowding and approaches to a certain limited value at high collector current due to current crowding and approaches to a certain limited value at high collector currents regardless of the emitter size. It is also observed that due to ac current crowding base capacitance increases with increasing collector current. To quantigy the ac crowding effects for SPICE circuit simulation the base capacitance(C$_b$) including the base depletion and diffusion components has been modeled with an analytical expression form.

• 한국정보통신학회논문지
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• 제11권11호
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• pp.2100-2106
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• 2007

[ $0.25{\mu}m$ ] N-well CMOS 공정기술을 이용하여 전류 구동형 A/D 변환기 회로를 설계하였다. 설계된 회로도에는 트랜스컨덕턴스(transconductance), 선형 폴더(folder) 회로 및 1 비트 A/D 변환기로 구성되어 있다. 트렌스컨덕턴스 회로를 이용하여 입력전압을 전류로 변환시킨 후 변환된 전류신호를 이용하여 선형성이 매우 양호한 폴더 회로를 얻을 수 있었다. 폴더 회로를 다단으로 종속접속시킴으로써 n비트 A/D 변환기로 확장할 수 있다. 본 연구에서 설계된 A/D 변환기는 대략 25MSPS으로 구동할 수 있는 6비트 A/D 변환기 회로이다.

• 품질경영학회지
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• 제46권4호
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• pp.1001-1014
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• 2018

Purpose: Autonomous driving cars, which are often represent the new convergence product, have been researched since the early years of 1900 but their safety assurance policies are yet to be implemented for real world practices. The primary purpose of this paper is to propose a modular concept based on which a safety assurance system can be designed and implemented for operating autonomous driving cars. Methods: We combine a set of key attributes of CE mark (European Assurance standard), E-Mark (Automobile safety assurance system), and A-SPICE (Automobile software assurance standard) into a modular approach. Results: Autonomous vehicles are emphasizing software safety, but there is no integrated safety certification standard for products and software. As such, there is complexity in the product and software safety certification process during the development phase. Using the concept of module, we were able to come up with an integrated safety certification system of product and software for practical uses in the future. Conclusion: Through the modular concept, both international and domestic standards policy stakeholders are expected to consider a new structure that can help the autonomous driving industries expedite their commercialization for the technology advanced market in the era of Industry 4.0.

• ETRI Journal
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• 제36권1호
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• pp.89-98
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• 2014

The integration of digital circuits has a tight relation with the scaling down of silicon technology. The continuous scaling down of the feature size of CMOS devices enters the nanoscale, which results in such destructive effects as short channel effects. Consequently, efforts to replace silicon technology with efficient substitutes have been made. The carbon nanotube field-effect transistor (CNTFET) is one of the most promising replacements for this purpose because of its essential characteristics. Various digital CNTFET-based circuits, such as standard logic cells, have been designed and the results demonstrate improvements in the delay and energy consumption of these circuits. In this paper, a new CNTFET-based 5-input XOR gate based on a novel design method is proposed and simulated using the HSPICE tool based on the compact SPICE model for the CNTFET at the 32-nm technology node. The proposed method leads to improvements in performance and device count compared to the conventional CMOS-style design.