JSTS:Journal of Semiconductor Technology and Science

  • 제14권4호
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  • Pages.463-470
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  • 2014
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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Verilog Modeling of Transmission Line for USB 2.0 High-Speed PHY Interface

  • Seong, Ki-Hwan (Department of Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH)) ;
  • Lim, Ji-Hoon (Department of Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH)) ;
  • Kim, Byungsub (Department of Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH)) ;
  • Sim, Jae-Yoon (Department of Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH)) ;
  • Park, Hong-June (Department of Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH))
  • 투고 : 2014.03.26
  • 심사 : 2014.06.10
  • 발행 : 2014.08.30
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초록

A Verilog model is proposed for transmission lines to perform the all-Verilog simulation of high-speed chip-to-chip interface system, which reduces the simulation time by around 770 times compared to the mixed-mode simulation. The single-pulse response of transmission line in SPICE model is converted into that in Verilog model by converting the full-scale analog signal into an 11-bit digital code after uniform time sampling. The receiver waveform of transmission line is calculated by adding or subtracting the single-pulse response in Verilog model depending on the transmitting digital code values with appropriate time delay. The application of this work to a USB 2.0 high-speed PHY interface reduces the simulation time to less than three minutes with error less than 5% while the mixed-mode simulation takes more than two days for the same circuit.

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참고문헌

  1. M. Choi et al. "A Channel Model of Scaled RCdominant Wires for High-Speed Wireline Transceiver Design", Journal of Semiconductor Technology and Science(JSTS), vol. 13, no. 5, pp. 482- 491, Oct. 2013. https://doi.org/10.5573/JSTS.2013.13.5.482
  2. M. Van Ierssel, H. Yamaguchi and A. Sheikholeslami, "Event-driven modeling of CDR jitter induced by power supply noise, finite decision-circuit bandwidth and channel ISI", IEEE Trans. Circuits Syst. I, vol. 55, no. 5, pp. 1306-1315, May. 2008. https://doi.org/10.1109/TCSI.2008.916454
  3. K. S. Kundert, "Predicting the phase noise and jitter of PLL-based frequency synthesizers", in Phase-Locking in High-Performance Systems : From Devices to Architectures. IEEE Press, 2003.
  4. Sabrina Liao et al., "A Verilog Piecewise-Linear Analog Behavior Model for Mixed-Signal Validation", IEEE Custom Integrated Circuits Conference (CICC), Sep. 2013.
  5. M. Park et al., "Fast and Accurate Event-Driven Simulation of Mixed-Signal Systems with Data Supplementation", IEEE Custom Integrated Circuits Conference (CICC), Sep. 2011.
  6. Mohammad Ashraf et al. "A FULL FUNCTION VERILOG PLL LOGIC MODEL", IEEE Custom Integrated Circuits Conference (CICC), Sep. 1997.
  7. "Spectre Circuit Simulator User Guide", Product Version 5.0, July 2002
  8. "USB2.0 Transceiver Macrocell Interface Specification, Revision 1.05," Intel, Hillsboro, OR, Mar. 29, 2001.
  9. S. Park et al., "A Single-Data-Bit Blind Oversampling Data-Recovery Circuit With an Add-Drop FIFO for USB2.0 High-Speed Interface," IEEE Trans. Circuits Syst. II, vol. 55, no. 2, pp. 156-160, Feb. 2008. https://doi.org/10.1109/TCSII.2007.911791

피인용 문헌

  1. EMI Issues in Pseudo-Differential Signaling for SDRAM Interface vol.15, pp.5, 2015, https://doi.org/10.5573/JSTS.2015.15.5.455
  2. All-Synthesizable Current-Mode Transmitter Driver for USB2.0 Interface vol.25, pp.2, 2017, https://doi.org/10.1109/TVLSI.2016.2600267