Browse > Article
http://dx.doi.org/10.4218/etrij.14.0113.0051

An Efficient 5-Input Exclusive-OR Circuit Based on Carbon Nanotube FETs  

Zarhoun, Ronak (Nanotechnology and Quantum Computing Laboratory, Shahid Beheshti University)
Moaiyeri, Mohammad Hossein (Nanotechnology and Quantum Computing Laboratory, Shahid Beheshti University)
Farahani, Samira Shirinabadi (Nanotechnology and Quantum Computing Laboratory, Shahid Beheshti University)
Navi, Keivan (Quantum Computing Laboratory, Shahid Beheshti University, Department of Electrical Engineering and Computer Science, University of California)
Publication Information
ETRI Journal / v.36, no.1, 2014 , pp. 89-98 More about this Journal
Abstract
The integration of digital circuits has a tight relation with the scaling down of silicon technology. The continuous scaling down of the feature size of CMOS devices enters the nanoscale, which results in such destructive effects as short channel effects. Consequently, efforts to replace silicon technology with efficient substitutes have been made. The carbon nanotube field-effect transistor (CNTFET) is one of the most promising replacements for this purpose because of its essential characteristics. Various digital CNTFET-based circuits, such as standard logic cells, have been designed and the results demonstrate improvements in the delay and energy consumption of these circuits. In this paper, a new CNTFET-based 5-input XOR gate based on a novel design method is proposed and simulated using the HSPICE tool based on the compact SPICE model for the CNTFET at the 32-nm technology node. The proposed method leads to improvements in performance and device count compared to the conventional CMOS-style design.
Keywords
Nanotechnology; carbon nanotube field-effect transistor; CNTFET; high-performance circuits; CNTFET-based inverter; exclusive-OR gate; XOR gate;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
1 G. Cho, Y. Kim, and F. Lombardi, "Assessment of CNTFET Based Circuit Performance and Robustness to PVT Variations," 52nd IEEE Int. Midwest Symp. Circuits Syst., Cancun, Mexico, Aug. 2-5, 2009, pp. 1106-1109.
2 M.H. Moaiyeri et al., "High-Performance Mixed-Mode Universal Min-Max Circuits for Nanotechnology," Circuits, Syst., Signal Process., vol. 31, no. 2, Apr. 2012, pp. 465-488.   DOI
3 M.H. Moaiyeri et al., "Efficient CNTFET-Based Ternary Full Adder Cells for Nanoelectronics," Nano-Micro Lett., vol. 3, no. 1, Apr. 2011, pp. 43-50.   DOI
4 M. Ghasemi et al., "A New SPICE Model for Organic Molecular Transistors and a Novel Hybrid Architecture," IEICE Electron. Exp., vol. 9, no. 10, May 2012, pp. 926-931.   DOI
5 G. Cho et al., "Performance Evaluation of CNFET-Based Logic Gates," Proc. IEEE Int. Instrum. Meas. Technol. Conf., Singapore, May 5-7, 2009, pp. 909-912.
6 N. Ahmed and R. Hasan, "A New Design of XOR-XNOR Gates for Low Power Application," Int. Conf. Electron. Dev., Syst. Appl., Kuala Lumpur, Malaysia, Apr. 25-27, 2011, pp. 45-49.
7 F. Chowdhury et al., "Novel Single-Device "XOR" AND "AND" Gates for High Speed, Very Low Power LSI Mechanical Processors," 16th Int. Solid-State Sensors, Actuators Microsyst. Conf., Beijing, China, June 5-9, 2011, pp. 1100-1103.
8 N. Burgess, "The Flagged Prefix Adder and Its Applications in Integer Arithmetic," J. VLSI Signal Process., vol. 31, no. 3, July 2002, pp. 263-271.   DOI
9 H.T. Bui, Y. Wang, and Y. Jiang, "Design and Analysis of Low- Power 10-Transistor Full Adders Using Novel XOR/XNOR Gates," IEEE Trans. Circuits Syst. II: Analog Dig. Signal Process., vol. 49, no. 1, Jan. 2002, pp. 25-30.   DOI
10 H. Lee and G.E. Sobelman, "New XOR/XNOR and Full Adder Circuits for Low Voltage, Low Power Applications," Microelectron. J., vol. 29, no. 8, Aug. 1998, pp. 509-517.   DOI   ScienceOn
11 J.M. Wang, S.C. Fang, and W.S. Feng, "New Efficient Designs for XOR and XNOR Functions on the Transistor Level," IEEE J. Solid-State Circuits, vol. 29, no. 7, July 1994, pp. 780-786.   DOI   ScienceOn
12 M.H. Moaiyeri et al., "Novel Direct Designs for 3-Input XOR Function for Low-Power and High-Speed Applications," Int. J. Electron., vol. 97, no. 6, Mar. 2010, pp. 647-662.   DOI
13 A. Reyhani-Masoleh and M. Hasan, "Low Complexity Bit Parallel Architectures for Polynomial Basis Multiplication over GF(2m)," IEEE Trans. Comput., vol. 53, no. 8, Aug. 2004, pp. 945-959.   DOI   ScienceOn
14 J. Wang et al., "Low Power and High Performance Dynamic CMOS XOR/XNOR Gate Design," Proc. 36th Int. Conf. Micro-, Nano-Eng., vol. 88, no. 8, Aug. 2011, pp. 2781-2784.
15 S. Goel, M.A. Elgamel, and M.A. Bayoumi, "Novel Design Methodology for High-Performance XOR-XNOR Circuit Design," Proc. 16th Symp. Integr. Circuits Syst. Des., Sao Paulo, Brazil, Sept. 8-11, 2003, pp. 71-76.
16 S. Mishra, A. Agrawal, and R. Nagaria, "A Comparative Performance Analysis of Various CMOS Design Techniques for XOR and XNOR Circuits," Int. J. Emerg. Technol., vol. 1, Feb. 2010, pp. 1-10.
17 M. Jamaa et al., "Programmable Logic Circuits Based on Ambipolar CNFET," Proc. 45th Annu. Des. Autom. Conf., Anaheim, CA, USA, June 8-13, 2008, pp. 339-340.
18 N. Patil et al., "Scalable Carbon Nanotube Computational and Storage Circuits Immune to Metallic and Mispositioned Carbon Nanotubes," IEEE Trans. Nanotechnol., vol. 10, no. 4, July 2011, pp.744-750.   DOI
19 M.R. Reshadinezhad, M.H. Moaiyeri, and K. Navi, "An Energy- Efficient Full Adder Cell Using CNFET Technology," IEICE Trans. Electron., vol. E95-C, no. 4, Apr. 2012, pp. 744-751.   DOI
20 S. Lin, Y. Kim, and F. Lombardi, "CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits," IEEE Trans. Nanotechnol., vol. 10, no. 2, Mar. 2011, pp. 217-225.   DOI
21 J. Deng, Device Modeling and Circuit Performance Evaluation for Nanoscale Devices: Silicon Technology beyond 45 nm Node and Carbon Nanotube Field Effect Transistors, doctoral dissertation, Stanford University, 2007.
22 H. Shahidipour, A. Ahmadi, and K. Maharatna, "Effect of Variability in SWCNT-Based Logic Gates," Proc. 12th Int. Symp. Integr. Circuits, Singapore, Dec. 14-16, 2009, pp. 252-255.
23 Y. Kim and F. Lombardi, "A Novel Design Methodology to Optimize the Speed and Power of the CNTFET Circuits," 52nd IEEE Int. Midwest Symp. Circuits Syst., Cancun, Mexico, Aug. 2-5, 2009, pp. 1130-1133.
24 J. Deng and H. Wong, "A Compact SPICE Model for Carbon- Nanotube Field-Effect Transistors including Nonidealities and Its Application -Part I: Model of the Intrinsic Channel Region," IEEE Trans. Electron Devices, vol. 54, no. 12, Dec. 2007, pp. 3186-3194.   DOI   ScienceOn
25 J. Deng and H. Wong, "A Compact SPICE Model for Carbon- Nanotube Field-Effect Transistors including Nonidealities and its Application -Part II: Full Device Model and Circuit Performance Benchmarking," IEEE Trans. Electron Devices, vol. 54, no. 12, Dec. 2007, pp. 3195-3205.   DOI
26 A. Lin et al., "Threshold Voltage and On-Off Ratio Tuning for Multiple-Tube Carbon Nanotube FETs," IEEE Trans. Nanotechnol., vol. 8, no. 1, Jan. 2009, pp. 4-9.   DOI
27 K.E. Zoiros et al., "Theoretical Analysis and Performance Investigation of Ultrafast All-Optical Boolean XOR Gate with Semiconductor Optical Amplifier-Assisted Sagnac Interferometer," Opt. Commun., vol. 258, no. 2, Feb. 2006, pp. 114-134.   DOI
28 S.F. Hsiao et al., "Automatic Generation of High-Performance Multiple-Input XOR/XNOR Circuits and Its Application in Advanced Encryption Standard (AES)," Int. Symp. Next- Generation Electron., Kaohsiung, Taiwan, Nov. 18-19, 2010, pp. 77-80.
29 P. McEuen, M.S. Fuhrer, and H. Park, "Single-Walled Carbon Nanotube Electronics," IEEE Trans. Nanotechnol., vol. 1, no. 1, Mar. 2002, pp. 78-85.   DOI   ScienceOn
30 M.D. Lewis, "114 MFLOPS Logarithmic Number System Arithmetic Unit for DSP Applications," IEEE J. Solid-State Circuits, vol. 30, no. 12, Dec. 1995, pp. 1547-1553.   DOI
31 J.H. Kim et al., "All-Optical XOR Gate Using Semiconductor Optical Amplifiers without Additional Input Beam," IEEE Photonics Technol. Lett., vol. 14, no. 10, Oct. 2002, pp. 1436- 1438.   DOI   ScienceOn
32 S. Lin, Y.B. Kim, and F. Lombardi, "A Novel CNTFET-Based Ternary Logic Gate Design," 52nd IEEE Int. Midwest Symp. Circuits Syst., Cancun, Mexico, Aug. 2-5, 2009, pp. 435-438.
33 S. Lin et al., "A New SRAM Cell Design Using CNTFETs," Int. SoC Design Conf., vol. 1, Busan, South Korea, Nov. 24-25, 2008, pp. 168-171.
34 A. Raychowdhury and K. Roy, "Carbon Nanotube Electronics: Design of High-Performance and Low-Power Digital Circuits," IEEE Trans. Circuits Syst I, Reg. Papers, vol. 54, no. 11, Nov. 2007, pp. 2391-2401.   DOI
35 Y.B. Kim, "Challenges for Nanoscale MOSFETs and Emerging Nanoelectronics," Trans. Electr. Electron. Mater., vol. 11, no. 3, June 2010, pp. 93-105.   DOI   ScienceOn
36 M.H. Moaiyeri, K. Navi, and O. Hashemipour, "Design and Evaluation of CNFET-Based Quaternary Circuits," Circuits, Syst., Signal Process., vol. 31, no. 5, Oct. 2012, pp. 1631-1652.   DOI
37 M.H. Moaiyeri et al., "Design and Analysis of a High- Performance CNFET-Based Full Adder," Int. J. Electron., vol. 99, no. 1, no. 1, Oct. 2012, pp. 113-130.   DOI