Verilog Modeling of Transmission Line for USB 2.0 High-Speed PHY Interface |
Seong, Ki-Hwan
(Department of Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH))
Lim, Ji-Hoon (Department of Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH)) Kim, Byungsub (Department of Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH)) Sim, Jae-Yoon (Department of Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH)) Park, Hong-June (Department of Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH)) |
1 | "Spectre Circuit Simulator User Guide", Product Version 5.0, July 2002 |
2 | Sabrina Liao et al., "A Verilog Piecewise-Linear Analog Behavior Model for Mixed-Signal Validation", IEEE Custom Integrated Circuits Conference (CICC), Sep. 2013. |
3 | M. Park et al., "Fast and Accurate Event-Driven Simulation of Mixed-Signal Systems with Data Supplementation", IEEE Custom Integrated Circuits Conference (CICC), Sep. 2011. |
4 | Mohammad Ashraf et al. "A FULL FUNCTION VERILOG PLL LOGIC MODEL", IEEE Custom Integrated Circuits Conference (CICC), Sep. 1997. |
5 | "USB2.0 Transceiver Macrocell Interface Specification, Revision 1.05," Intel, Hillsboro, OR, Mar. 29, 2001. |
6 | S. Park et al., "A Single-Data-Bit Blind Oversampling Data-Recovery Circuit With an Add-Drop FIFO for USB2.0 High-Speed Interface," IEEE Trans. Circuits Syst. II, vol. 55, no. 2, pp. 156-160, Feb. 2008. DOI ScienceOn |
7 | M. Choi et al. "A Channel Model of Scaled RCdominant Wires for High-Speed Wireline Transceiver Design", Journal of Semiconductor Technology and Science(JSTS), vol. 13, no. 5, pp. 482- 491, Oct. 2013. DOI ScienceOn |
8 | M. Van Ierssel, H. Yamaguchi and A. Sheikholeslami, "Event-driven modeling of CDR jitter induced by power supply noise, finite decision-circuit bandwidth and channel ISI", IEEE Trans. Circuits Syst. I, vol. 55, no. 5, pp. 1306-1315, May. 2008. DOI ScienceOn |
9 | K. S. Kundert, "Predicting the phase noise and jitter of PLL-based frequency synthesizers", in Phase-Locking in High-Performance Systems : From Devices to Architectures. IEEE Press, 2003. |
![]() |