• ETRI Journal
• /
• v.14 no.4
• /
• pp.194-209
• /
• 1992

애널로그 회로 시뮬레이터인 HSPICE에 대한 사용자 인터페이스 시스팀을 개발하였다. 이 시스팀은 HSPICE 가 탑재된 컴퓨터와 TCP/IP 네트워크로 연결된 시스팀에서 HSPICE를 사용할 수 있도록 하는 네트워크 인터페이스 기능과 HSPICE 출력 데이터를 실제 신호 파형으로 그래픽 처리해서 분석할 수 있게 하는 사용자 인터페이스 기능을 제공한다. HSPICE 사용자가 아닌 일반 SPICE 사용자들도 출력데이터를 HSPICE 의 Graph Data File의 형태로 변환시켜 주면 사용자 인터페이스 기능을 이용해서 출력 데이터의 그래픽 처리 및 분석이 가능하다.

• Proceedings of the Acoustical Society of Korea Conference
• /
• autumn
• /
• pp.171-174
• /
• 2004

본 논문은 Hspice 를 사용한 달팽이관 생역학의 능동적이며 선형적인 1 차 그리고 2 차원 모델링을 보여준다. Hspice 모델링의 장점은 달팽이관 생역학을 아날로그 IC 칩으로 구현할 수 있다는 점이다. 즉 Biochip 으로 설계하는데 활용된다. 본 논문은 달팽이관 생역학을 어떻게 전기회로 모델화한 뒤, 다시 어떻게 Hspice 코드로 표현하는 가를 보여준다. 달팽이관 회로가 Hspice 코드 실행을 위해 변형되어야만 하는 과정을 상세히 보여준다. 1 차원의 결과와 2 차원의 결과를 비교하고 있다.

• The Journal of the Acoustical Society of Korea
• /
• v.24 no.3E
• /
• pp.77-86
• /
• 2005

This paper shows one and two dimensional active linear modeling of cochlear biomechanics using Hspice. The advantage of the Hspice modeling is that the cochlear biomechanics may be implemented into an analog Ie chip. This paper explains in detail how to transform the physical cochlear biomechanics to the electrical circuit model and how to represent the circuit in Hspice code. There are some circuit design rules to make the Hspice code to be executed properly.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.35D no.7
• /
• pp.63-71
• /
• 1998

Generally, electronic packaging designer uses HSPICE SOFTWARE TOOL to validate electric characteristics of traces layout before layout traces in PCB in hundreds Mb/s high speed digital circuits. We are in need of a plated through hole (PTH) model and a connector model to use HSPICE SOFTWARE TOOL. Those models have not been perfectly defined for HSPICE simulation. In this paper, we define a PTH model and a connector model for HSPICE simulation and discuss application range for these models. Th emodels are analytic models very applicable for HSPICE simulation and are used to analyze electric characteristic of the PTH and the connector in thetraces layout in high speed digital circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.8
• /
• pp.105-113
• /
• 2004

MRAM uses magneto-resistance material as a storage element, which stores cell data as a polarization of spin in a free magnetic layer. This magneto-resistance material has hysteresis, asteroid curve at the thermal variation, and R-V characteristics for switching the data. Therefore, a macro-model which can reproduce these characteristics is required for MRAM simulation. We propose a macro-model of TMR (Tunneling Magneto Resistance) that can reproduce all of these characteristics on HSPICE. Also we propose a novel sensing scheme, which generates reference resistance having the medium value, ( $R_{H}$+ $R_{L}$)/2, for a wide range of applied voltage and present simulation results based on the HSPICE macro-model of MTJ that we have developed.d.d.

• Journal of Korea Society of Industrial Information Systems
• /
• v.16 no.5
• /
• pp.1-8
• /
• 2011

This paper proposes a new input pattern generator for minimal leakage power in the nanometer CMOS technology considering all the leakage current components (sub-threshold leakage, gate tunneling leakage, band-to-band tunneling leakage). Using the accurate macro-model, a heuristic algorithm is developed to generate a input pattern for the minimum leakage. The algorithm applies to ISCAS85 benchmark circuits, and the results are compared with the results of Hspice. The simulation result shows that our method's accuracy is within a 5% difference of the Hspice simulation results. In addition, the simulation time of our method is far faster than that of the Hspice simulation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2003.10a
• /
• pp.385-388
• /
• 2003

In this paper, a D-Latch is replaced by a memory cell on the proposed PFD to improve response tine by reducing reset me. The PFD has been simulated using HSPICE with a Hynix 0.35um CMOS process to prove the performance improvement.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.13 no.9
• /
• pp.1837-1844
• /
• 2009

In this paper, the circuit of 2 variable ternary adder and multiplier circuit using current mode CMOS are implemented. The presented ternary adder circuit and multiplier circuit using current mode CMOS are driven the voltage levels. We show the characteristics of operation for these circuits simulated by HSpice. These circuits are simulated under $0.18{\mu}m$ CMOS standard technology, $5{\mu}A$ unit current in $0.54{\mu}m/0.18{\mu}m$ ratio of NMOS length and width, and $0.54{\mu}m/0.18{\mu}m$ ratio of PMOS length and width, and 2.5V VDD voltage, MOS model Level 47 using HSpice. The simulation results show the satisfying current characteristics. The simulation results of current mode ternary adder circuit and multiplier circuit show the propagation delay time $1.2{\mu}s$, operating speed 300KHz, and consumer power 1.08mW.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.4 s.334
• /
• pp.45-52
• /
• 2005

This paper presents the characterization of through hole vias on printed circuit board (PCB) through the time domain and frequency domain measurements. The time domain measurement was performed on a single via using the TDR, and the model parameters were extracted by the fitting simulation using HSPICE. The frequency domain measurement was also performed by using 2 port VNA, and the model parameters were extracted by fitting simulation with ADS. Using the ABCD matrices, the do-embedding equations were derived probing in the same plane in the VNA measurement. Based on the single via characterization, the differential via characterization was also performed by using TDR measurements. The time domain measurements were performed by using the odd mode and even mode sources in TDR module, and the Parameter values were extracted by fitting with HSPICE. Comparing measurements with simulations, the maximum calculated differences were $14\%$ for single vias and $17\%$ for differential vias.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.2
• /
• pp.67-75
• /
• 2004

This paper presents a buffer insertion method for RLC-class interconnect structured as a sin91e line or a tree. First, a closed form expression for the interconnect delay of a CMOS buffer driving single RLC line is represented. This expression has been derived by the n-th power law for deep submicrometer technology and occurs to be within 9 percentage of maximal relative error in accuracy compared with the results of HSPICE simulation for various RLC loads. This paper proposes a closed form expression based on this for the buffer insertion of single RLC lines and the buffer sizing algorithms for RLC tree interconnects to optimize path delays. The proposed buffer insertion algorithms are applied to insert buffers for several interconnect trees with a 0.25${\mu}{\textrm}{m}$ CMOS technology and the results are compared against those of HSPICE.