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http://dx.doi.org/10.6109/JKIICE.2009.13.9.1837

Implementation of Ternary Valued Adder and Multiplier Using Current Mode CMOS  

Seong, Hyeon-Kyeong (상지대학교 컴퓨터정보공학부)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.13, no.9, 2009 , pp. 1837-1844 More about this Journal
Abstract
In this paper, the circuit of 2 variable ternary adder and multiplier circuit using current mode CMOS are implemented. The presented ternary adder circuit and multiplier circuit using current mode CMOS are driven the voltage levels. We show the characteristics of operation for these circuits simulated by HSpice. These circuits are simulated under $0.18{\mu}m$ CMOS standard technology, $5{\mu}A$ unit current in $0.54{\mu}m/0.18{\mu}m$ ratio of NMOS length and width, and $0.54{\mu}m/0.18{\mu}m$ ratio of PMOS length and width, and 2.5V VDD voltage, MOS model Level 47 using HSpice. The simulation results show the satisfying current characteristics. The simulation results of current mode ternary adder circuit and multiplier circuit show the propagation delay time $1.2{\mu}s$, operating speed 300KHz, and consumer power 1.08mW.
Keywords
Current-mode CMOS; Termary logic circuit; Finite Fields GF(3); Adder; Multiplier;
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