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A Buffer Insertion Method for RLC Interconnects  

김보겸 (숭실대학교 컴퓨터학과)
김승용 (숭실대학교 컴퓨터학과)
김석윤 (숭실대학교 컴퓨터학과)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.41, no.2, 2004 , pp. 67-75 More about this Journal
Abstract
This paper presents a buffer insertion method for RLC-class interconnect structured as a sin91e line or a tree. First, a closed form expression for the interconnect delay of a CMOS buffer driving single RLC line is represented. This expression has been derived by the n-th power law for deep submicrometer technology and occurs to be within 9 percentage of maximal relative error in accuracy compared with the results of HSPICE simulation for various RLC loads. This paper proposes a closed form expression based on this for the buffer insertion of single RLC lines and the buffer sizing algorithms for RLC tree interconnects to optimize path delays. The proposed buffer insertion algorithms are applied to insert buffers for several interconnect trees with a 0.25${\mu}{\textrm}{m}$ CMOS technology and the results are compared against those of HSPICE.
Keywords
Terms-Inductance; interconnect; buffer insertion; tree;
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