Journal of Korea Society of Industrial Information Systems (한국산업정보학회논문지)

Korea Society of Industrial Information Systems (한국산업정보학회)
권호 표지
DOI QR코드

DOI QR Code

Minimal Leakage Pattern Generator

  • 김경기 (대구대학교 정보통신대학 전자공학부)
  • Published : 2011.12.30
Download PDF
⟨ Previous Next ⟩

Abstract

This paper proposes a new input pattern generator for minimal leakage power in the nanometer CMOS technology considering all the leakage current components (sub-threshold leakage, gate tunneling leakage, band-to-band tunneling leakage). Using the accurate macro-model, a heuristic algorithm is developed to generate a input pattern for the minimum leakage. The algorithm applies to ISCAS85 benchmark circuits, and the results are compared with the results of Hspice. The simulation result shows that our method's accuracy is within a 5% difference of the Hspice simulation results. In addition, the simulation time of our method is far faster than that of the Hspice simulation.

Keywords

References

  1. N. Verma, "Analysis Towards Minimization of Total SRAM Energy Over Active and Idle Operating Modes ", IEEE Tran. on Very Large Scale Integration (VLSI) Systems, Vol. 19, Issue 9, pp. 1695-1703, Sept. 2011. https://doi.org/10.1109/TVLSI.2010.2055906
  2. A. Agarwal, S. Mukhopadhyay, C.H.Kim, et al., "Leakage power analysis and reduction: models, estimation and tools", IEE Proceedings - Computers and Digital Tech- niques, Volume 152, Issue 3, Page(s) 353-368, May 2005. https://doi.org/10.1049/ip-cdt:20045084
  3. S. G. Narendra, A. Chandrakasan, "Leakage in Nanometer CMOS Technologies (Series on Integrated Circuits and sytems)", Springer, Nov. 2005.
  4. Y. Wang, X. Chen, W. Wang, Y. Cao, Y. Xie, H. Yang, "Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques", IEEE Tran. on Very Large Scale Integration (VLSI) Systems, Vol. 19, Issue 4, pp. 615-628, April. 2011. https://doi.org/10.1109/TVLSI.2009.2037637
  5. Feng Gao, John P. Hayes, "Exact and Heuristic Approaches to Input Vector Control for Leakage Power Reduction, Computer Aided Design", ICCAD-2004, Page(s)527-532, Nov. 2004.
  6. Xiaotao Chang, Dongrui Fan, et al., "Soc Leakage Power Reduction Algorithm by Input Vector Control", System-on- Chip,2005, Page(s)86-89, Nov. 2005.
  7. D. Shurin, E. Kvaktun, A. Fish, "Input Vector Control efficiency in sub-micron CMOS technologies," IEEEI 2010, pp. 569-573, Nov. 2010.

Cited by

  1. 나노 MOSFET 공정에서의 초저전압 NCL 회로 설계 vol.17, pp.4, 2011, https://doi.org/10.9723/jksiis.2012.17.4.017
  2. NCL 기반의 저전력 ALU 회로 설계 및 구현 vol.18, pp.5, 2011, https://doi.org/10.9723/jksiis.2013.18.5.059