• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.365-368
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• 2002

WSW(Wrap Side Wall) is proposed to decrease junction electric field in this paper. WSW process is fabricated after first gate etch, followed NMI ion implantation and deposition & etch nitride layer New WSW structure has buffer layer to decrease electric field. Also we compared the hot carrier characteristics of WSW and conventional. Also, we design a test pattern including pulse generator, level shifter and frequency divider, so that we can evaluate AC hot carrier degradation on-chip.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.5-8
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• 2002

Hot carrier induced device degradation is observed in thin-film, gate-all-around SOI transistor under DC stress conductions. We observed the more significant device degradation in GAA device than general single gate SOI device due to the degradation of edge transistor. Therefore, it is expected that the maximum available supply voltage of GAA transistor is lower than that o( bulk MOSFET or single gale SOI device.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.363-366
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• 1998

25.deg. C 에서 120.deg. C까지 온도를 증가시키면서 hot carrier effect에 의한 nMOSFET의 degradation을 drain current와 transconductance의 변화를 통해 알아보았다. 온도가 증가할수록 hot carrier에 의한 degradation 이 전체적으로 줄어드는 것을 볼수 있었다. stress를 가한 후 reverse mode로 측정하였는데 saturation 영역보다 linear 영역에서 drain current의 degradation이 크게 나탔으며 온도가 증가할수록 이러한 경향이 유지되면서 degradation이 감소하였다. transconductance는 linear 영역과 saturation 영역에서 각각 측정하였는데 온도가 증가할수록 linear 영역의 degradation이 더많이 감소하였다.

• 전자공학회논문지A
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• 제31A권1호
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• pp.93-102
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• 1994

This paper, presents SECRET(SEC REliability Tool), which predicts reliability problems related to the hot-carrier and electromigration effects on the submicron MOSFETs and interconnections. To simulate DC and AC lifetime for hot-carrier damaged devices, we have developed an accurate substrate current model with the geometric sensitivity, which has been verified over the wide ranges of transistor geometries. A guideline can be provided to design hot-carrier resistant circuits by the analysis of HOREL(HOT-carrier RFsistant Logic) effect, and circuit degradation with respect to physical parameter degradation such as the threshold voltage and the mobility can also be expected. In SECRET, DC and AC MTTF values of metal lines are calculated based on lossy transmission line analysis, and parasitic resistances, inductances and capacitances of metal lines are accurately considered when they operate in the condition of high speed. Also, circuit-level reliability simulation can be applied to the determination of metal line width and-that of optimal capacitor size in substrate bias generation circuit. Experimental results obtained from the several real circuits show that SECERT is very useful to estimate and analyze reliability problems.

• 전자공학회논문지D
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• 제34D권12호
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• pp.39-45
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• 1997

This study presents the first experimental data for the impact of hot-carrier degradtion on the performance of CMOS folded-cascode op-amps. A folded-cascode op-amp which has an NMOS input pair has been designed and fabricated using a 0.8.mu.m single-poly, double-metal CMOS process. After high voltage stress, the degradtion of perfomrance parameters such as open-metal CMOS process. After high voltage stress, the degradation of performance parameters such as open-loop voltage gain, unity-gain frequency and phase margin has been analized and physically explaniend in terms of hot carrier degradation.

• 전자공학회논문지A
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• 제33A권4호
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• pp.129-135
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• 1996

In this paper, the hot carrier effect and device degradation of deep submicrometer SC-PMOSFETs have been measured and characterized. It has been shown that the substrate current of a 0.15$\mu$m PMOSFET increases with increasing of impact ionization rate, and the impact ionization rate is a function of the gate length and gate bias voltage. Correlation between gate current and substrate current is investigated within the general framework of the lucky-electron. It is found that the impact ionization rate increases, but the device degradation is not serious with decreasing effective channel length. SCIHE is suggested as the possible phusical mechanism for enhanced impact ionization rate and gate current reduction. Considering the hot carrier induced device degradation, it has been found that the maximum supply voltage is about -2.6V for 0.15$\mu$m PMOSFET.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1997년도 추계학술대회 논문집
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• pp.266-269
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• 1997

Hot carrier effects as a function of bias stress time and bias stress conditions were syste-matica1ly investigated in p-channel po1y-Si TFT's fabricated on the quartz substrate. The device degradation was observed for the negative bias stress. After positive bias stressing, Improvement of electrical characteristic except for subthreshold slope was observed. It was found that these results were related to the hot carrier injection into the gate oxide and interface states at the poly-Si/SiO$_2$interface rather than defects states generation under bias stress.

• 전자공학회논문지D
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• 제36D권5호
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• pp.21-28
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• 1999

Deep Submicron 영역에서 요구되는 고성능 소자로서 자기-정렬된 ESD(Elevated Source/Drain)구조의 MOSFET을 제안하였다. 제안된 ESD 구조는 일반적인 LDD(Lightly-Doped Drain)구조와는 달리 한번의 소오스/드레인 이온주입 과정이 필요하며, 건식 식각 방법을 적용하여 채널의 함몰 깊이를 조정할 수 있는 구조를 갖는다. 또한 제거가 가능한 질화막 측벽을 최종 질화막 측벽의 형성 이전에 선택적인 채널 이온주입을 위한 마스크로 활용하여 hot-carrier 현상을 감소시켰으며, 반전된 질화막 측벽을 사용하여 기존이 ESD 구조에서 문제시될 수 있는 자기-정렬의 문제를 해결하였다. 시뮬레이션 결과, 채널의 함몰 깊이 및 측벽의 넓이를 조정함으로써 충격이온화율(ⅠSUB/ID) 및 DIBL(Drain Induced Barrier Lowering) 현상을 효과적으로 감소시킬 수 있고, 유효채널 길이에 따라 차이가 있으나 두 번의 질화막 측벽을 사용함으로써 hot-carrier 현상이 개선될 수 있음을 확인하였다.

• 한국전기전자재료학회논문지
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• 제15권1호
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• pp.1-6
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• 2002

The hot carried degradation in a metal oxide semiconductor device has been one of the most serious concerns for MOS-ULSI. In this paper, three types of LDD(lightly doped drain) structure for suppression of hot carried degradation, such as decreasing of performance due to spacer-induced degradation and increase of series resistance will be investigated. in this study, LDD-nMOSFETs used had three different drain structure, (1) conventional surface type LDD(SL), (2) Buried type LDD(BL), (3) Surface implantation type LDD(SI). As experimental results, the surface implantation the LDD structure showed that improved hot carrier lifetime to comparison with conventional surface and buried type LDD structures.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.199-200
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• 2005

In this paper, the electrical characteristics and hot-carrier induced electrical performance degradations of high-voltage LDMOSFET fabricated by the existing CMOS technology were investigated. Different from the low voltage CMOS device, the only specific on-resistance was degraded due to hot-carrier stressing in LDMOS transistor. However, other electrical parameters such as threshold voltage, transconductance, and saturated drain current were not degraded after stressing. The amount of on-resistance degradation of LDMOS transistor that was implanted n-well with $1.0\times10^{13}/cm^2$ was approximately 1.6 times more than that of LDMOS transistor implanted n-well with $1.0\times10^{12}/cm^2$. Similar to low voltage CMOS device, the peak on-resistance degradation in LDMOS device was observed at gate voltage of 2.2V while the drain applied voltage was 50V. It means that the maximum impact ionization at the drain junction occurs at the gate voltage of 2.2V applying the drain voltage of 50V.