Circuit-Level Reliability Simulation and Its Applications

회로 레벨의 신뢰성 시뮬레이션 및 그 응용

This paper, presents SECRET(SEC REliability Tool), which predicts reliability problems related to the hot-carrier and electromigration effects on the submicron MOSFETs and interconnections. To simulate DC and AC lifetime for hot-carrier damaged devices, we have developed an accurate substrate current model with the geometric sensitivity, which has been verified over the wide ranges of transistor geometries. A guideline can be provided to design hot-carrier resistant circuits by the analysis of HOREL(HOT-carrier RFsistant Logic) effect, and circuit degradation with respect to physical parameter degradation such as the threshold voltage and the mobility can also be expected. In SECRET, DC and AC MTTF values of metal lines are calculated based on lossy transmission line analysis, and parasitic resistances, inductances and capacitances of metal lines are accurately considered when they operate in the condition of high speed. Also, circuit-level reliability simulation can be applied to the determination of metal line width and-that of optimal capacitor size in substrate bias generation circuit. Experimental results obtained from the several real circuits show that SECERT is very useful to estimate and analyze reliability problems.