• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.1033-1036
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• 1999

This paper proposes an efficient fault diagnosis for digital circuits using multilayer neural networks. The efficient learning algorithm is also proposed for the multilayer neural network, which is combined the steepest descent for high-speed optimization and the dynamic tunneling for global optimization. The fault-diagnosis system using the multilayer neural network of the proposed algorithm has been applied to the parity generator circuit. The simulation results shows that the proposed system is higher convergence speed and rate, in comparision with system using the backpropagation algorithm based on the gradient descent.

• Progress in Superconductivity
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• v.9 no.2
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• pp.157-161
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• 2008

Due to high speed operations and ultra low power consumptions RSFQ logic circuit is a very good candidate for future electronic device. The focus of the RSFQ circuit development has been on the advancement of analog-to-digital converters and microprocessors. Recent works on RSFQ ALU development showed the successful operation of an 1-bit block of ALU at 40 GHz. Recently, the study of an RSFQ analog-to-digital converter has been extended to the development of a single chip RF digital receiver. Compared to the voltage logic circuits, RSFQ circuits operate based on the pulse logic. This naturally leads the circuit structure of RSFQ circuit to be pipelined. Delay time on each pipelined stage determines the ultimate operating speed of the circuit. In simulations, a two junction Josephson transmission line's delay time was about 10 ps, a splitter's 14.5 ps, a switch's 13 ps, a half adder's 67 ps. Optimization of the 4-bit ALU circuit has been made with delay time consideration to operate comfortably at 10 GHz or above.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.58 no.4
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• pp.623-626
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• 2009

In this paper, we applied new analog viterbi decoder to decode PR(1,2,2,1) signal for DVD and analyze the specific and signal characteristics. We implemented the parallel analog viterbi decoder and the convolution digital viterbi decoder(the digital PRML) utilizing the technology of analog parallel processing circuits. The proposed analog viterbi decoder can replace the conventional digital viterbi decoder by a new one. Our circuits design the low distortion and the high accuracy over the previous implementation. Through the parallel structure of the proposed viterbi decoder, we got the achievement of the decoding speed by the multiple times.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1185-1187
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• 1987

Digital systems are increasingly being used in the ranges of many control engineering. The residue number system offers the possibility of high speed operation and error correction. The compact self-checking pulse-train residue arithmetic circuit is proposed. A fault tolerant digital filter is practically implemented using these proposed circuits.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.477-483
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• 2015

The k-Winners-Take-All (kWTA) is an operation to find the largest k (>1) inputs among N inputs. Parallel search algorithm of kWTA for digital inputs is not invented yet, so most of digital kWTA architectures have O(N) time complexity. A parallel search algorithm for digital kWTA operation and the circuits for its VLSI implementation are presented in this paper. The proposed kWTA architecture can compare all inputs simultaneously in parallel. The time complexity of the new architecture is O(logN), so that it is scalable to a large number of digital data. The high-speed kWTA operation and its O(logN) dependency of the new architecture are verified by simulations. It takes 290 ns in searching for 5 winners among 1024 of 32 bit data, which is more than thousands of times faster than existing digital kWTA circuits, as well as existing analog kWTA circuits.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.11a
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• pp.23-27
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• 2000

Simultaneous Switching Noise (SSN) propagated through parallel power and ground planes in high-speed multilayer printed circuit boards (PCBs) causes malfunction of both digital and analog circuits. To reduce SSN, decoupling capacitors are generally used in the PCBs. In this paper, we improve the equivalent circuit model of decoupling capacitor in high-frequency range to analyze the effect of SSN reduction accurately. The analysis is performed by the microwave and RF design system (MDS) method and the finite difference time domain (FDTD) method. We compared the results by the ideal capacitor model with those by the proposed model.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.55-60
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• 2011

Most of neural network chips use an analog-type maximum selector circuit (MS). As the increase of integration level, the analog MS has difficulties in achieving sufficient resolution. Contrary, the digital-type MS is easy to get high resolution but slower than its analog counterparts. A new high-speed digital MS circuit called MSIT (Maximum Selector with Internal Trigger-signal) is presented in this paper. The MSIT has been designed to achieves both the high reliability by using trigger-signals and high speed by removing the unnecessary waiting times. The response time of MSIT is 3.4ns for 32 data with 10-bit resolution in the simulation with 1.2V, $0.13{\mu}m$-process model parameters, which is much faster than its analog counterparts. It shows that digital MS circuits like MSIT can achieve higher speed as well as higher resolution than analog MS circuits.

• Progress in Superconductivity and Cryogenics
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• v.8 no.1
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• pp.26-28
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• 2006

The development technique of digital logic using CMOS device is close reached several limitations These make technical needs that are ultra high speed superconductive systems based on CMOS silicon digital computing technique. Comparing digital logic based on silicon CMOS, the computing technique based on ultra high speed superconductive systems has many advantages which are ultra low power consumption, ultra high operation speed. etc. It is estimated that features like these increasingly improve the possibility of ultra low power and ultra superconductive systems. In this paper digital logics of current CMOS technique and RSFQ superconductive technique are compared with and analyzed.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.195-198
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• 2000

It is possible to perform the digital fuzzy logical high-speed and high-precision computation by the use of redundantly-represented binary positive-digit number arithmetic operation. In this paper, as basic operation circuits in the fuzzy logic new voltage-mode 4-valued binary parallel processing operation circuits using positive redundantly-expressed binary-coded numbers is discussed.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.8
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• pp.933-939
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• 2008

In this paper, a new composite electromagnetic bandgap(EBG) structure using magnetic materials is proposed for simultaneous switching noise(SSN) suppression in the high-speed digital circuits. The proposed EBG structure has periodic unit cells of square-patches connected by spiral-shaped bridges. The magnetic materials are located on the unit cells of spiral-shaped EBG. The real part of the permeability shifts bandgap to the lower frequency region due to the increased effective inductance. The imaginary part of the permeability has magnetic loss that decreases parasitic LC resonance peaks from between the unit cells. As a result, the proposed structure has the lower cut-off frequency compared with conventional EBG structure and -30 dB SSN suppression bandwidth from 175 MHz to 7.7 GHz. The proposed structure is expected to improve the power integrity and reduce the size of the EBG power plane.