Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Development of A High-Speed Digital Maximum Selector Circuit With Internal Trigger-Signal Generator

내부 트리거 발생회로를 이용한 고속의 디지털 Maximum Selector 회로의 설계

  • 윤명철 (단국대학교(천안) 전자공학과)
  • Received : 2011.01.04
  • Published : 2011.02.25
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Abstract

Most of neural network chips use an analog-type maximum selector circuit (MS). As the increase of integration level, the analog MS has difficulties in achieving sufficient resolution. Contrary, the digital-type MS is easy to get high resolution but slower than its analog counterparts. A new high-speed digital MS circuit called MSIT (Maximum Selector with Internal Trigger-signal) is presented in this paper. The MSIT has been designed to achieves both the high reliability by using trigger-signals and high speed by removing the unnecessary waiting times. The response time of MSIT is 3.4ns for 32 data with 10-bit resolution in the simulation with 1.2V, $0.13{\mu}m$-process model parameters, which is much faster than its analog counterparts. It shows that digital MS circuits like MSIT can achieve higher speed as well as higher resolution than analog MS circuits.

그동안 신경망칩의 설계에는 주로 아날로그 Maximum Selector (MS) 회로를 사용하였다. 그러나 집적도가 높아질수록 아날로그 MS회로는 신호의 해상도(Resolution)을 높이는데 어려움이 있다. 반면 디지털 MS 회로는 높은 해상도를 얻기는 쉬우나 속도가 느린 단점이 있었다. 본 논문에서는 신경망칩의 디지털화에 사용하기 위한 MSIT(Maximum Selector with Internal Trigger-Signal) 라는 고속의 디지털 MS회로를 개발하였다. MSIT는 제어신호 발생기를 내장하여 안정적인 동작을 확보하고, 불필요한 대기시간을 없애도록 이를 최적화 함으로써 높은 속도를 얻을 수 있다. 1.2V-$0.13{\mu}m$ 프로세스의 모델파라메터를 사용하여 32 개의 10 비트 데이터에 대하여 시뮬레이션을 수행한 결과 3.4ns의 응답시간을 얻을 수 있었다. 이는 동급의 해상도를 갖는 아날로그 MS회로 보다 훨씬 빠른 속도로써, MSIT와 같은 디지털 MS 회로가 아날로그 MS회로에 비하여 높은 해상도와 빠른 속도를 구현할 수 있음을 보여준다.

Keywords

References

  1. J. Lazzaro, S. Ryckebusch, M. A. Mahowald, and C. A. Mead, D. S. Touretzky, Winner-Take- All Networks of O(n) Complexity, vol. 1, pp.703 -711 1989 :Morgan Kaufmann.
  2. A. G. Andreou, K. A. Boahen, A. Pavasovic, P. O. Pouliquen, R. E. Jenkins, and K. Strohbehn, "Current-mode subthreshold MOS circuits for analog VLSI neural systems", IEEE Trans. Neural Netw., vol. 2, no. 2, pp.205-213 1991. https://doi.org/10.1109/72.80331
  3. P. O. Pouliquen, A. G. Andreou, K. Strohbehn, and R. E. Jenkins, "An associative memory integrated system for character recognition", Proc. 36th Midwest Symp. Circuits Systems, pp.762-765 1993.
  4. J. A. Startzyk and X. Fang, "CMOS current-mode winner-take-all circuit with both excitatory and inhibitory feedback", Electron. Lett., vol. 29, no. 10, pp.908-910 1993. https://doi.org/10.1049/el:19930606
  5. S. P. DeWeerth and T. G. Morris, "CMOS current-mode winner-take-all circuit with distributed hysteresis", Electron. Lett., vol. 31, no. 13, pp.1051-1053 1995. https://doi.org/10.1049/el:19950729
  6. G. Indiveri, "A current-mode hysteretic winner-take-all network, with excitatory and inhibitory coupling", Analog Integr. Circuits Signal Process., vol. 28, pp.279 -291 2001. https://doi.org/10.1023/A:1011208127849
  7. D. M. Wilson and S. P. DeWeerth, "Winning isn't everything", Proc. IEEE ISCAS'95, pp.105 -108 1995.
  8. R. Kalim and D. M. Wilson, "Semi-parallel rank-order filtering in analog VLSI", Proc. IEEE ISCAS'99, vol. 2, pp.232 -235 1999.
  9. Fish, A. Milrud, V. Yadid-Pecht, O., "Highspeed and high-precision current winner-takeall circuit," Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 52, no. 3, pp. 131-135, March 2005.
  10. S. M. Jung, S. Shin, H.. Baik, and M. S. Park, "New fast successive elimination algorithm", Proc. IEEE MWSCAS2000, pp. 616-619, 2000.
  11. Kapralski, A., "The maximum and minimum selector SELRAM and its application for developing fast sorting machines," Computers, IEEE Transactions on, vol. 38, no. 11, pp. 1572-1577, Nov 1989. https://doi.org/10.1109/12.42127
  12. Shibata, T. Nakada, A. Konda, M. Morimoto, T. Ohmi, T. Akutsu, H. Kawamura, and A. Marumoto, K., "A fully-parallel vector quantization processor for real-time motion picture compression" IEEE ISSCC97, pp. 270-271, 1997.
  13. Nozawa, T. Konda, M. Fujibayashi, M. Imai, M. Ohmi, T., "A parallel vector quantization processor eliminating redundant calculations for real-time motion picture compression" IEEE J. Solid State Circuits,, vol. 35, no.11, pp. 1774-1751, 2000.
  14. Ogawa, M.; Ito, K.; Shibata, T., "A generalpurpose vector-quantization processor employing two-dimensional bit-propagating winner-takeall" IEEE Sym. VLSI Circuits Digest of Tech. Papers, vol. 35, no.11, pp. 244-247, 2002.
  15. The MOSIS Service, http://www.mosis.com/ Technical/Testdata [Online]
  16. Rahman, M.; Baishnab, K.L.; Talukdar, F.A., "A high speed and high resolution VLSI Winner-take-all circuit for neural networks and fuzzy systems" IEEE ISSCC2009, pp. 1-4, 2009.