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Development of A High-Speed Digital Maximum Selector Circuit With Internal Trigger-Signal Generator  

Yoon, Myung-Chul (Department of Electronics Engineering, Dankook University)
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Abstract
Most of neural network chips use an analog-type maximum selector circuit (MS). As the increase of integration level, the analog MS has difficulties in achieving sufficient resolution. Contrary, the digital-type MS is easy to get high resolution but slower than its analog counterparts. A new high-speed digital MS circuit called MSIT (Maximum Selector with Internal Trigger-signal) is presented in this paper. The MSIT has been designed to achieves both the high reliability by using trigger-signals and high speed by removing the unnecessary waiting times. The response time of MSIT is 3.4ns for 32 data with 10-bit resolution in the simulation with 1.2V, $0.13{\mu}m$-process model parameters, which is much faster than its analog counterparts. It shows that digital MS circuits like MSIT can achieve higher speed as well as higher resolution than analog MS circuits.
Keywords
Maximum-Selector; Winner Takes All; Neural Network; Digital Maximum Selector; Digital Integrated Ciruit;
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1 D. M. Wilson and S. P. DeWeerth, "Winning isn't everything", Proc. IEEE ISCAS'95, pp.105 -108 1995.
2 R. Kalim and D. M. Wilson, "Semi-parallel rank-order filtering in analog VLSI", Proc. IEEE ISCAS'99, vol. 2, pp.232 -235 1999.
3 Fish, A. Milrud, V. Yadid-Pecht, O., "Highspeed and high-precision current winner-takeall circuit," Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 52, no. 3, pp. 131-135, March 2005.
4 S. M. Jung, S. Shin, H.. Baik, and M. S. Park, "New fast successive elimination algorithm", Proc. IEEE MWSCAS2000, pp. 616-619, 2000.
5 Kapralski, A., "The maximum and minimum selector SELRAM and its application for developing fast sorting machines," Computers, IEEE Transactions on, vol. 38, no. 11, pp. 1572-1577, Nov 1989.   DOI   ScienceOn
6 Shibata, T. Nakada, A. Konda, M. Morimoto, T. Ohmi, T. Akutsu, H. Kawamura, and A. Marumoto, K., "A fully-parallel vector quantization processor for real-time motion picture compression" IEEE ISSCC97, pp. 270-271, 1997.
7 Nozawa, T. Konda, M. Fujibayashi, M. Imai, M. Ohmi, T., "A parallel vector quantization processor eliminating redundant calculations for real-time motion picture compression" IEEE J. Solid State Circuits,, vol. 35, no.11, pp. 1774-1751, 2000.
8 Ogawa, M.; Ito, K.; Shibata, T., "A generalpurpose vector-quantization processor employing two-dimensional bit-propagating winner-takeall" IEEE Sym. VLSI Circuits Digest of Tech. Papers, vol. 35, no.11, pp. 244-247, 2002.
9 The MOSIS Service, http://www.mosis.com/ Technical/Testdata [Online]
10 J. Lazzaro, S. Ryckebusch, M. A. Mahowald, and C. A. Mead, D. S. Touretzky, Winner-Take- All Networks of O(n) Complexity, vol. 1, pp.703 -711 1989 :Morgan Kaufmann.
11 S. P. DeWeerth and T. G. Morris, "CMOS current-mode winner-take-all circuit with distributed hysteresis", Electron. Lett., vol. 31, no. 13, pp.1051-1053 1995.   DOI   ScienceOn
12 A. G. Andreou, K. A. Boahen, A. Pavasovic, P. O. Pouliquen, R. E. Jenkins, and K. Strohbehn, "Current-mode subthreshold MOS circuits for analog VLSI neural systems", IEEE Trans. Neural Netw., vol. 2, no. 2, pp.205-213 1991.   DOI   ScienceOn
13 P. O. Pouliquen, A. G. Andreou, K. Strohbehn, and R. E. Jenkins, "An associative memory integrated system for character recognition", Proc. 36th Midwest Symp. Circuits Systems, pp.762-765 1993.
14 J. A. Startzyk and X. Fang, "CMOS current-mode winner-take-all circuit with both excitatory and inhibitory feedback", Electron. Lett., vol. 29, no. 10, pp.908-910 1993.   DOI   ScienceOn
15 G. Indiveri, "A current-mode hysteretic winner-take-all network, with excitatory and inhibitory coupling", Analog Integr. Circuits Signal Process., vol. 28, pp.279 -291 2001.   DOI   ScienceOn
16 Rahman, M.; Baishnab, K.L.; Talukdar, F.A., "A high speed and high resolution VLSI Winner-take-all circuit for neural networks and fuzzy systems" IEEE ISSCC2009, pp. 1-4, 2009.