Browse > Article
http://dx.doi.org/10.5573/JSTS.2015.15.4.477

A Parallel Search Algorithm and Its Implementation for Digital k-Winners-Take-All Circuit  

Yoon, Myungchul (Department of Electronics Engineering, Dankook University)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.15, no.4, 2015 , pp. 477-483 More about this Journal
Abstract
The k-Winners-Take-All (kWTA) is an operation to find the largest k (>1) inputs among N inputs. Parallel search algorithm of kWTA for digital inputs is not invented yet, so most of digital kWTA architectures have O(N) time complexity. A parallel search algorithm for digital kWTA operation and the circuits for its VLSI implementation are presented in this paper. The proposed kWTA architecture can compare all inputs simultaneously in parallel. The time complexity of the new architecture is O(logN), so that it is scalable to a large number of digital data. The high-speed kWTA operation and its O(logN) dependency of the new architecture are verified by simulations. It takes 290 ns in searching for 5 winners among 1024 of 32 bit data, which is more than thousands of times faster than existing digital kWTA circuits, as well as existing analog kWTA circuits.
Keywords
k-winners-take-all; digital k-WTA circuit; parallel k-WTA; parallel search algorithm; scalable k-WTA architecture;
Citations & Related Records
연도 인용수 순위
  • Reference
1 C. A. Marinov and J. J. Hopfield, "Stable computational dynamics for a class of circuits with O(N) interconnections capable of KWTA and rank extractions". IEEE Trans. Circuit. Syst., vol.52, no.5, pp. 949-959, 2005.   DOI   ScienceOn
2 M. Rahman, K. L. Baishnab, and F. A. Talukdar, "A high speed and high resolution VLSI Winnertake-all circuit for neural networks and fuzzy systems" IEEE ISSCC2009, pp. 1-4, 2009.
3 A. Fish, D. Akselrod, and O. Yadid-Pecht, "High precision image centroid computation via an adaptive k-winner-take-all circuit in conjunction with a dynamic element matching algorithm for star tracking applications". Analog Integ. Circuit. Signal Process. vol. 39, pp. 251-266, 2004.   DOI   ScienceOn
4 A. K. J. Hertz and R. G. Palmer, Introduction to the Theory of Neural Computation, Redwood City, Addison-Wesley, 1991.
5 D. Tian, Y. Liu, and D. Wei, "A Dynamic Growing Neural Network for Supervised or Unsupervised Learning," Intelligent Control and Automation, WCICA 2006, vol.1, pp. 2886-2890, 2006.
6 U. Cilingiroglu and T. L. E. Dake, "Rank-order filter design with a sampled-analog multiplewinners-take-all core," IEEE J. Solid-State Circuits, vol. 37, no. 2, pp. 978-984, Aug. 2002.   DOI   ScienceOn
7 L. Itti, C. Koch, and E. Niebur, "A model of saliency-based visual attention for rapid scene analysis," IEEE Trans. Pattern Analysis and Machine Intelligence, vol. 20, no. 11, pp. 1254-1259, Nov. 1998.   DOI   ScienceOn
8 T. Eltoft and R. I. P. deFigueiredo, "A new neural network for cluster-detection-and-labeling," IEEE Trans. Neural Networks, vol. 9, no. 5, pp. 1021-1035, 1998.   DOI   ScienceOn
9 K. Urahama and T. Nagao, "K-winners-take-all circuit with 0(N) complexity," IEEE Trans. Neural Networks, vol. 6, pp. 776-778, May 1995.   DOI   ScienceOn
10 Z. Guo and J.Wang, "Information retrieval from large data sets via multiple-winners-take-all," Circuits and Systems (ISCAS2011) pp. 2669-2672, May 2011.
11 B. Sekerkiran, and U. Cilingiroglu, "A CMOS Kwinners-take-all circuit with O(n) complexity," IEEE Trans. Circuits and Systems II, vol. 46, no. 1, pp. 1-5, 1999.
12 Y. Hung, C. Y. Tsai, and B. D. Liu, "1-V rail-torail analog CMOS programmable winner-take-all chip with two-side searching capability for neurocomputing applications," in Proc. Neural Networks and Signal Processing, vol.1, pp. 337-340, 2003.
13 P.V. Tymoshchuk, "A fast analogue K-winnerstake-all neural circuit," in Proc. Neural Networks (IJCNN), pp.1-8, 2013.
14 N. Kumar, P. O. Pouliquen, and A. G. Andreou, "Device mismatch limitations on the performance of a Hamming distance classifier" in Proc. Defect and Fault Tolerance in VLSI Systems, pp. 327-334 1993.
15 P. V. Tymoshchuk, and M. P. Tymoshchuk, "Stability and convergence analysis of model state variable trajectories of analogue KWTA neural circuit," in Proc. Direct and Inverse Problems of Electro-magnetic and Acoustic Wave Theory, pp. 26-35, 2011.
16 C. S. Lin, P. Ou, and B. D. Liu, "Design of k-WTA/Sorting Network Using Maskable WTA/MAX Circuit". In Proc. VLSI Symposium on Technology, Systems and Applications, pp. 69-72, June 2001.
17 A. Kapralski, "The maximum and minimum selector SELRAM and its application for developing fast sorting machines," IEEE Trans. Computers, vol. 38, no. 11, pp. 1572-1577, 1989.   DOI   ScienceOn
18 M. Ogawa, K. Ito, and T. Shibata, "A generalpurpose vector- quantization processor employing two-dimensional bit-propagating winner-take-all" IEEE Sym. VLSI Circuits Digest of Tech. Papers, vol. 35, no.11, pp. 244-247, 2002.
19 T. C. Hsu and S. D. Wang, "k-Winners-take-all neural net with O(1) time complexity". IEEE Trans. Neural Networks. vol. 8, no. 6, pp. 1557-1561, 1997.   DOI   ScienceOn
20 H. Y. Li, C. M. Ou, Y.T. Hung, W. J. Hwang, and C. L. Hung, "Hardware Implementation of k-Winner-Take-All Neural Network with On-chip Learning," in Proc. Computational Science and Engineering, pp. 340-345, Dec. 2010.