• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.12-17
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• 2011

In this work, the analog performances of n-MOSFET fabricated on strained-Si/relaxed Si buffer layer with Ge mole fractions and thermal annealing temperatures after device fabrication have been characterized in Depth. The effective electron mobility was increased with the increase of Ge mole fraction for all annealing temperatures. However the effective electron mobility was decreased at the Ge mole fraction of 32%. The analog performances were enhanced with the increase of Ge mole fraction at the room temperature but they were degraded at the Ge mole fraction of 32%. Since the degradation of the effective electron mobility of strained-Si layer is more significant than one of conventional Si layer at elevated temperature, the degradation of analog performances of SGOI devices were increased than those of SOI devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.101-102
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• 2009

SGOI MOSFETs with various Ge mole fractions were fabricated and compared to the SOI MOSFET. SGOI MOSFETs have a lager drain current and higher effective mobility than the SOI MOSFET as increased Ge mole fractions. The lattice constant difference causes lattice mismatch between the SiGe layer and the top-Si layer during the top-Si layer growth. However, SGOI MOSFETs have a lager leakage current at subthreshold region. Also, leakage current at subthreshold region increased with Ge mole fractions. This is attributable to the crystalline defects due to the lattice mismatch between the SiGe layer and the top-Si layer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.99-100
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• 2009

SGOI 1T-DRAM cells with various Ge mole fractions were fabricated and compared to the SOI 1T-DRAM cell. SGOI 1T-DRAM cells have a higher leakage current than SOI 1T-DRAM cell at subthreshold region. The leakage current due to crystalline defects and interface states at Si/SiGe increased with Ge mole. This phenomenon causes sensing margin and the retention time of SGOI 1T-DRAMs decreased with increase of Ge mole fraction.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.1-7
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• 2004

In order to enhance the electron mobility in SOI n-MOSFET, we fabricated fully depletion(FD) n-MOSFET on the strained Si/relaxed SiGa/SiO$_2$/Si structure(strained Si/SGOI) formed by inserting SiGe layer between a buried oxide(BOX) layer and a top silicon layer. The summated thickness of the strained Si and relaxed SiGe was fixed by 12.8 nm and then the dependency of electron mobility on strained Si thickness was investigated. The electron mobility in the FD n-MOSFET fabricated on the strained Si/SGOI enhanced about 30-80% compared to the FD n-MOSFET fabricated on conventional SOI. However, the electron mobility decreased with the strained Si thickness although the inter-valley phonon scattering was reduced via the enhancement of the Ge mole fraction. This result is attributed to the increment of intra-valley phonon scattering in the n-channel 2-fold valley via the further electron confinement as the strained Si thickness was reduced.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.449-452
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• 1998

We have studied the oxidatio nrte of $Si_{1-x}Ge_{x}$ epitaxial layer grown by MBE(molecular beam epitaxy). Oxidation were performed at 700.deg. C, 800.deg. C, 900.deg. C, and 1000.deg. C. After the oxidation, the results of AES(auger electron spectroscopy) showed that Ge was completely rejected out of the oxide and pile up at $SiO_{2}/$Si_{1-x}Ge_{x}$ interface. It is shown that the presence of Ge at the $SiO_{2}$/$Si_{1-x}Ge_{x}$ interface changes the dry oxidation rate. The dry oxidation rate was equal to that of pure Si regardless of Ge mole fraction at 700.deg. C and 800.deg.C, while it was decreased at both 900.deg. C and 1000.deg.C as the Ge mole fraction was increased. The ry oxidation rates were reduced for heavy Ge concentration, and large oxidation time. In the parabolic growth region of $Si_{1-x}Ge_{x}$ oxidation, The parabolic rate constant are decreased due to the presence of Ge-rich layer. After the longer oxidation at the 1000.deg.C, AES showed that Ge peak distribution at the $SiO_{2}$/$Si_{1-x}Ge_{x}$ interface reduced by interdiffusion of silicon and germanium.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.3 s.333
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• pp.9-16
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• 2005

The mobility in strained Si inversion layer on $Si_{1-x}Ge_x$ is calculated considering a quantum effect(subband energy and wavefunction) in inversion layer and relaxation time approximation. The quantum effect in inversion layer is obtained by using self-consistent calculation of $Schr\ddot{o}dinger$ and Poisson equations. For the relaxation time, intravalley and intervalley scatterings are considered. The result shows that the reason for the enhancement in mobility as Ge mole fraction increases is that the electron mobility in 2-폴드 valleys is about 3 times higher than that of 4-폴드 valleys and most electrons are located in 2-폴드 valleys as Ge mole fraction increases. Meanwhile, for the phonon-limited mobility the fitting to experimental data, Coulomb and surface roughness mobilities are included in total mobility, Deformation potentials are selected for the calculated effective field, temperature, and Ge mole fraction dependent mobilities to be fitted to experimental data, and then upgraded data can be obtained by considering nonparabolicity in Si band structure.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.12
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• pp.1080-1086
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• 2005

We have studied the Ge redistribution after dry oxidation and the oxide growth rate of $Si_{1-x}Ge_x$ epitaxial layer. Oxidation were performed at 700, 800, 900, and $1,000\;^{\circ}C$. After the oxidation, the results of RBS (Rutherford Back Scattering) & AES(Auger Electron Spectroscopy) showed that Ge was completely rejected out of the oxide and pile up at $Si_{1-x}Ge_x$ interface. It is shown that the presence of Ge at the $Si_{1-x}Ge_x$ interface changes the dry oxidation rate. The dry oxidation rate was equal to that of pure Si regardless of Ge mole fraction at 700 and 800$^{\circ}C$, while it was decreased at both 900 and $1,000^{\circ}C$ as the Ge mole fraction was increased. The dry of idation rates were reduced for heavy Ge concentration, and large oxiidation time. In the parabolic growth region of $Si_{1-x}Ge_x$ oxidation, the parabolic rate constant are decreased due to the presence of Ge-rich layer. After the longer oxidation at the $1,000^{\circ}C$, AES showed that Ge peak distribution at the $Si_{1-x}Ge_x$ interface reduced by interdiffusion of silicon and germanium.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.60-60
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• 2003

디자인 룰에 의해 Gate Length 가 100nm 이하로 줄어듦에 따라 Gate delay 감소와 Switch speed 향상을 위해 보다 더 큰 drive current 를 요구하게 되었다. 본 연구는 dirve current 를 증가시키기 위해 고안된 Strained Si substrate 를 만들기 위한 SiGe layer 성장에 관한 연구이다. SiGe layer를 성장시킬 때 SiH$_4$ gas와 GeH$_4$ gas를 furnace에 flow시켜 Chemical 반응에 의해 Si Substrate를 성장시키는 LPCVD(low pressure chemical vapor depositio)법을 사용하였고 SIMS와 nanospec을 이용하여 박막 두께 및 Ge concentration을 측정하였고, AFM으로 surface의 roughness를 측정하였다. 본 연구에서 우리는 10,20,30,40%의 Ge concentration을 갖는 10nm 이하의 SiGe layer를 얻기 위하여 l0nm 이하의 fixed 된 두께로 SiGe layer를 성장시킬 때 temperature, GeH$_4$ gas pre-flow, SiH$_4$ 와 GeH$_4$의 gas ratio를 변화시켜 성장시킨 후 Ge 의 concentration과 실제 형성된 두께를 측정하였고, SiGe의 mole fraction의 변화에 따른 surface의 roughness 를 측정하였다. 그 결과 10 nm의 두께에서 temperature, GeH$_4$ gas pre-flow, SiH$_4$ 와 GeH$_4$ 의 gas ratio의 변화와 Ge concentration 과의 의존성을 확인 할 수 있었고, SiGe 의 mole traction이 증가하였을 때 surfcace의 roughness 가 증가함을 알 수 있었다. 이 연구 결과는 strained Si 가 가지고 있는 strained Si 내에서 n-FET 와 P-FET사이의 불균형에 대한 해결과 좀 더 발전된 형태인 fully Depleted Strained Si 제작에 기여할 것으로 보인다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.190-191
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• 2006

We have investigated optical properties of Si/graded-$Si_{1-x}Ge_x$/Si heterostructures grown by reduced pressure chemical vapor deposition. Compared to standard condition using Si(100) substrate and growth temperature of $650^{\circ}C$, Si(111) resulted in low growth rate and high Ge mole fraction. Also samples grown at higher temperatures exhibited increased growth rate and reduced Ge mole fraction. The features regarding both substrate temperature and crystal orientation, representing high incorporation of silicon supplied from gas stream played as a key parameter, illustrate that reaction control were prevailed in this process growth condition. Using secondary ion mass spectroscopy and spectroscopic ellipsometry, microscopic changes in atomic components could be analyzed for Si/graded-$Si_{1-x}Ge_x$/Si heterostructures.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.64.2-64.2
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• 2011

Recently, Silicon Germanium (SiGe) alloys have been received considerable attention for their great potentials in advanced electronic and optoelectronic devices. Especially, microcrystalline SiGe is a good channel material for thin film transistor due to its advantages such as narrow and variable band gap and process compatibility with Si based integrated circuits. In this work, microcrystalline silicon-germanium films (${\mu}c$-SiGe) were deposited by DC/RF magnetron co-sputtering method using Si and Ge target on Corning glass substrates. The film composition was controlled by changing DC and RF powers applied to each target. The substrate temperatures were changed from $100^{\circ}C$ to $450^{\circ}C$. The microstructure of the thin films was analyzed by x-ray diffraction (XRD) and Raman spectroscopy. The analysis results showed that the crystallinity of the films enhances with increasing Ge mole fraction. Also, crystallization temperature was reduced to $300^{\circ}C$ with $H_2$ dilution. Hall measurements indicated that the electrical properties were improved by Ge alloying.