• 융합정보논문지
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• 제11권7호
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• pp.104-110
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• 2021

본 핀 채널 전계 효과 트랜지스터에서 낮은 소스/드레인 직렬 저항을 위한 새로운 선택적 산화 방식을 제안하였다. 이 방법을 이용하면, gate-all-around 구조와 점진적으로 증가되는 형태의 소스/드레인 확장영역을 갖는 핀 채널 MOSFET를 얻을 수 있다. 제안된 트랜지스터는 비교 소자에 비해 70% 이상의 소스/드레인 직렬 저항의 감소를 얻을 수 있다. 또한, 제안된 소자는 단채널 효과를 억제하면서도 높은 구동 전류와 전달컨덕턴스 특징을 보인다. 제작된 소자의 포화전류, 최대 선형 전달컨덕턴스, 최대 포화 전달컨덕턴스, subthreshold swing, 및 DIBL은 각각 305 ㎂/㎛, 0.33 V, 13.5 𝜇S, 76.4 𝜇S, 78 mV/dec, 62 mV/V의 값을 갖는다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1995년도 춘계학술대회 논문집
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• pp.86-89
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• 1995

In this pacer, The effect of the impedances in SNOSEFT s memory devices has been developed. The effect of source and drain impedances are measuring using the method of the field effect bias resistance in the inner resistance regions of the device structure and external bias resistance. The effect of impedance by source and drain resistance shows according to increasing to the storage of memory charges, shows according to a function of decreasing to the gate voltages, shows the delay of threshold voltages, The delay time of low conductance state and high conductance state by the impedance effect shows 3 [${\mu}$sec] and 1[${\mu}$sec] respectively.

• Biotechnology and Bioprocess Engineering:BBE
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• 제6권4호
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• pp.252-263
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• 2001

Nematode infections compromise human health and reduce agricultural productivtiy. Experiments that exploit the powerful molecular genetics of the free-living nematode Caenorhabdl - elegans have contributed to our understanding of how the major classes of anthelmintic nema-tocides kill worms and how worms might evolve resistance to these drugs In C. elegans, as in parasites, benzimidixoles interfere with microtubule polyumerization the imidazothiazoles/tetra-hydropyrimidines activate nicotinic acetylcholine receptors, and the macrocyclic la ctones activate qlutamate-gate chloride chanels. Mutant alleles of genes that encode drug targes often confer resistance in C. elegans. Preliminary evidence suggests that alleles of homologous genes in parasites will, in many cases, also play a role in resistance. Thus information acquired from C. elegans can be usefully applied to understand the mechanisms of drug sensitivity and the genetics of resis-tance in parasites.

• 반도체디스플레이기술학회지
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• 제2권2호
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• pp.17-20
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• 2003

The current drive in an MOSFET is limited by the intrinsic channel resistance. All the other parasitic elements in a device structure playa significant role and degrade the device performance. These other resistances need to be less than 10%-20% of the channel resistance. To achieve the requirements, we should investigate a methodology of separation and quantification of those resistances. In this paper, we developed the extraction method of resistances using calibrated TCAD simulation. The resistance of the extension region is also partially determined by the formation of a surface accumulation region that forms under the gate in the tail region of the extension profile.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.481-482
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• 2006

We fabricated pentacene organic thin film transistor with good uniformity. And we extracted contact resistance in organic thin film transistors from the plot of the inverse of drain current versus channel length by extrapolating the curve to a channel length of zero, and multiplying by drain-source voltage. Extracted contact resistance is about $70K{\Omega}$ at gate-drain voltage of -20 V

• 한국전기전자재료학회논문지
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• 제13권2호
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• pp.170-176
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• 2000

The joints with multi-interfaces was expected to have low DC resistance compared with those with single interface. The small size joint specimens joined with Nb3Sn sub-cables were fabricated to investi-gate the DC performance in the range of 0 to 600A transport current without external magnetic field. The joints with multi-interfaces have a few n-Ohm resistance, which is much lower than that of single lap joint. Because the interfaces between sub-cables of multi-interfaced joint are more complicated than those of single-interfaced joint, the soldering condition between sub-cables is very effective on the joint DC resistance.

• 한국전기전자재료학회논문지
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• 제24권10호
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• pp.794-798
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• 2011

This paper was carried out design of 1,700 V Base Resistance Thyristor for fabrication. We decided conventional BRT (base resistance thyristor) device and Trench Gate type one for design. we carried out device and process simulation with T-CAD tools. and then, we have extracted optimal device and process parameters for fabrication. we have analysis electrical characteristics after simulations. As results, we obtained 2,000 V breakdown voltage and 3.0 V Vce,sat. At the same time, we carried out field ring simulation for obtaining high voltage.

• 한국전기전자재료학회논문지
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• 제32권4호
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• pp.272-275
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• 2019

We investigated the electrical characteristics of amorphous silicon-zinc-tin-oxide (a-SZTO) thin films deposited by RF-magnetron sputtering at room temperature depending on the deposition time. We fabricated a thin film transistor (TFT) with a bottom gate structure and various channel thicknesses. With increasing channel thickness, the threshold voltage shifted negatively from -0.44 V to -2.18 V, the on current ($I_{on}$) and field effect mobility (${\mu}_{FE}$) increased because of increasing carrier concentration. The a-SZTO film was fabricated and analyzed in terms of the contact resistance and channel resistance. In this study, the transmission line method (TLM) was adopted and investigated. With increasing channel thickness, the contact resistance and sheet resistance both decreased.

• 대한전자공학회논문지SD
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• 제41권12호
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• pp.27-34
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• 2004

최근 실리콘 미세공정의 발달로 상용화된 0.2$\mum$ 게이트길이 이하의 deep submicron MOSFET 출력특성을 정확히 모델링하기 위해서는 RF 기판 회로 연구가 필수적이다. 먼저 본 논문에서는 기판 캐패시던스와 기판 저항이 병렬로 연결된 모델과 기판 저항만을 사용한 단순 모델들에 적합한 직접 추출 방법을 각각 개발하였다. 이 추출방법들을 0.15$\mum$ CMOS 소자에 적용한 결과 단순 모델보다 RC 병렬 기판모델이 측정된 $Y_{22}$-parameter에 30GHz까지 더 잘 일치하는 것을 확인하였으며, 이는 RC 병렬 기판모델 및 직접추출방법의 RF 정확도를 증명한다. 이러한 RC 병렬 기판모델을 사용하여 게이트 길이를 0.11에서 0.5$\mum$까지 변화시키고 드레인 전압을 0에서 1.2V까지 증가시키면서 기판 모델 파라미터들의 bias 종속 특성과 게이트 길이 종속 특성을 새롭게 추출하였다. 이러한 새로운 추출 결과는 scalable한 RF 비선형 기판 모델 개발에 유용하게 사용될 것이다.

• 대한전자공학회논문지SD
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• 제49권2호
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• pp.9-14
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• 2012

본 연구에서는 common source-bulk와 common source-gate 테스트 구조에서 측정된 S-파라미터를 사용하여 multi-finger RF MOSFET의 기판 파라미터들을 정확하게 추출하였다. 이 추출 방법을 바탕으로 세 개의 기판저항을 사용한 비대칭 RF 모델이 하나의 기판저항을 사용한 단순 모델보다 측정된 Y-파라미터 데이터와 더 잘 일치하는 것을 관찰하였으며, 이는 비대칭 기판 모델의 정확도를 증명한다. 또한 비대칭 RF 모델의 시뮬레이션 S-파라미터가 측정 데이터와 20GHz까지 잘 일치하는 것을 확인하였다.