• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.100-106
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• 2010

The impact of surface quantization on device parameters of a Si metal oxide semiconductor (MOS) capacitor has been analyzed in the present work. Variation of conduction band bending, position of discrete energy states, variation of surface potential, and the variation of inversion carrier concentration at charge centroid have been analyzed for different gate voltages, substrate doping concentrations and oxide thicknesses. Oxide thickness calculated from the experimental C-V data of a MOS capacitor is different from the actual oxide thickness, since such data include the effect of surface quantization. A correction factor has been developed considering the effect of charge centroid in presence of surface quantization at strong inversion and it has been observed that the correction due to surface quantization is crucial for highly doped substrate with thinner gate oxide.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.339-339
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• 2012

현재 MOS 소자에 사용되고 있는 $SiO_2$ 산화막은 그 두께가 얇아짐에 따라 Gate Leakage current와 여러 가지 신뢰성 문제가 대두되고 있고, 이를 극복하고자 High-k물질을 사용하여 기존에 발생했던 Gate Leakage current와 신뢰성 문제를 해결하고자 하고 있다. 본 실험에서는 High-k(hafnium) Gate Material에 온도 변화를 주었을 때 여러 가지 전기적인 특성 변화를 보는 방향으로 연구를 진행하였다. 기본적인 P-Type Si기판을 가지고, 그 위에 있는 자연적으로 형성된 산화막을 제거한 후 Hafnium Gate Oxide를 Atomic Layer Deposition (ALD)를 이용하여 증착하고, Aluminium을 전극으로 하는 MOS-Cap 구조를 제작한 후 FGA 공정을 진행하였다. 마지막으로 $300^{\circ}C$, $450^{\circ}C$로 30분정도씩 Annealing을 하여, 온도 조건이 다른 3가지 종류의 샘플을 준비하였다. 3가지 샘플에 대해서 각각 I-V (Gate Leakage Current), C-V (Mobile Charge), Interface State Density를 분석하였다. 그 결과 Annealing 온도가 올라가면 Leakage Current와 Dit(Interface State Density)는 감소하고, Mobile Charge가 증가하는 것을 확인할 수가 있었다. 본 연구는 향후 High-k 물질에 대한 공정 과정에서의 다양한 열처리에 따른 전기적 특성의 변화 대한 정보를 제시하여, 향후 공정 과정의 열처리에 대한 방향을 잡는데 도움이 될 것이라 판단된다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.17-24
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• 2004

Quantum effects in the poly-gate are analyzed in two dimensions using the density-gradient method, and their impact on the short-channel effect of double-gate MOSFETs is investigated. The 2-D effects of quantum mechanical depletion at the gate to sidewall oxide is identified as the cause of large charge-dipole formation at the corner of the gate. The bias dependence of the charge dipole shows that the magnitude of the dipole peak-value increases in the subthreshold region and there is a large difference in carrier and potential distribution compared to the classical solution. Using evanescent-nude analysis, it is found that the quantum effect in the poly-gate substantially increases the short-channel effect and it is more significant than the quantum effect in the Si film. The penetration of potential contours into the poly-gate due to the dipole formation at the drain side of the gate corner is identified as the reason for the substantial increase in short-channel effects.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1502-1504
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• 1996

The effects of electrical stress in hydrogen passivated and as-fabricated poly-Si TFT's are investigated. It is observed that the charge trapping in the gate dielectric is the dominant degradation mechanism in poly-Si TFT's which has been stressed by the gate bias alone while the creation of defects in the poly-Si film is prevalent in gate and drain bias stressed devices. The degradation due to the gate bias stress is dramatically reduced with hydrogenation time while the degradation due to the gate and drain bias stress is increased a little. From the experimental results, it is considered that hydrogenation suppress the charge trapping at gate dielectrics as well as improve the characteristics of poly-Si TFT's.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.844-847
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• 2001

In this work, transient characteristics of the Non-Punch Through(NPT) Insulated Gate Bipolar Transistor(IGBT) has been studied. we has analyzed with lifetimes excess minority carrier injected into N-dirft, base region of IGBT's BJT part and accumulated charge of on-state which affected swiching characteristic. In this paper, excess minority carrier and charge distribution in active base region is expressed analytically. This analysis proposed optical trade-off between lifetimes and accumulated charge for decreasing switching losses because charge result in switching loss when device was tuned off.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.10
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• pp.665-671
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• 2017

Herein, we report the fabrication of low-voltage N-type organic field-effect transistors by using high capacitance fluorinated polymer gate dielectrics such as P(VDF-TrFE), P(VDF-TrFE-CTFE), and P(VDF-TrFE-CFE). Electron-withdrawing functional groups in PVDF-based polymers typically cause the depletion of negative charge carriers and a high contact resistance in N-channel organic semiconductors. Therefore, we incorporated intermediate layers of a low-k polymerto prevent the formation of a direct interface between PVDF-based gate insulators and the semiconducting active layer. Consequently, electron depletion is inhibited, and the high charge resistance between the semiconductor and source/drain electrodes is remarkably improved by the in corporation of solution-processed charge injection layers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.379-383
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• 2003

The subthreshold characteristics of Double-Gate MOSFETs are analyzed for various Tsi. In the lightly-doped asymmetric device, it is found that the subthreshold current dramatically increases as the Tsi increases and this phenomenon is due to the linear distribution of potential in the channel region with low depletion-charge. Further, we derived an analytical equation which can explain this phenomenon and verified the accuracy of analytical equation by comparing with the result of device simulation.

• 한국정보디스플레이학회:학술대회논문집
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• 2000.01a
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• pp.15-16
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• 2000

The gate bias stress effect of the hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) with a $SiN_x/BCB$ gate insulator have been studied. The gate planarization was carried out by spin-coating of BCB (benzocyclobutene) on Cr gates. The BCB exhibits charge trappings during a high gate bias, but the stability of the TFT is the same as conventional one when it is between -25 V and +25 V. The charge trap density in the BCB increases with its thickness.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.239-242
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• 1998

Ca $F_2$ films have superior gate insulator properties than conventional gate insulator such as $SiO_2$, Si $N_{x}$, $SiO_{x}$, and T $a_2$ $O_{5}$ to the side of lattice mismatch between Si substrate and interface trap charge density( $D_{it}$). Therefore, this material is enable to apply Thin Film Transistor(TFT) gate insulator. Most of gate oxide film have exhibited problems on high trap charge density, interface state in corporation with O-H bond created by mobile hydrogen and oxygen atom. This paper performed Ca $F_2$ property evaluation as MIM, MIS device fabrication. Ca $F_2$ films were deposited at the various substrate temperature using a thermal evaporation. Ca $F_2$ films was grown as polycrystalline film and showed grain size variation as a function of substrate temperature and RTA post-annealing treatment. C-V, I-V results exhibit almost low $D_{it}$(1.8$\times$10$^{11}$ $cm^{-1}$ /le $V^{-1}$ ) and higher $E_{br}$ (>0.87MV/cm) than reported that formerly. Structural analysis indicate that low $D_{it}$ and high $E_{br}$ were caused by low lattice mismatch(6%) and crystal growth direction. Ca $F_2$ as a gate insulator of TFT are presented in this paper paperaper

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.8
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• pp.605-610
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• 2010

The devices based on electrically erasable programmable read-only memory (EEPROM) structure are proposed for the detection of external electric charges. A large size charge contact window (CCW) extended from the floating gate is employed to immobilize external charges, and a control gate with stacked metal-insulator-metal (MIM) capacitor is adapted for a standard single polysilicon CMOS process. When positive voltage is applied to the capacitor of CCW of an n-channel EEPROM, the drain current increases due to the negative shift of its threshold voltage. Also when a pre-charged external capacitor is directly connected to the floating gate metal of CCW, the positive charges of the external capacitor make the drain current increase for n-channel, whereas the negative charges cause it to decrease. For an p-channel, however, the opposite behaviors are observed by the external voltage and charges. With the attachment of external charges to the CCW of EEPROM inverter, the characteristic inverter voltage behavior shifts from the reference curve dependent on external charge polarity. Therefore, we have demonstrated that the EEPROM inverter is capable of detecting external immobilized charges on the floating gate. and these devices are applicable to sensing the pH's or biomolecular reactions.