• Journal of the Korean Institute of Telematics and Electronics A
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• 제32A권6호
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• pp.41-50
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• 1995

A state-of-the-arts GaAs power metal semiconductor field effect transistor (MESFET) for 3.3V operation digital hand-held phone at 900 MHz has been developed for the first time, The FET was fabricated using a low-high doped structures grown by molecular beam epitaxy (MBE). The fabricated MESFETs with a gate width of 16 mm and a gate length of 0.8 .mu.m shows a saturated drain current (Idss) of 4.2A and a transconductance (Gm) of around 1700mS at a gate bias of -2.1V, corresponding to 10% Idss. The gate-to-drain breakdown voltage is measured to be 28 V. The rf characteristics of the MESFET tested at a drain bias of 3.3 V and a frequencyof 900 MHz are the output power of 32.3 dBm, the power added efficiency of 68%, and the third-ordr intercept point of 49.5 dBm. The power MESFET developed in this work is expected to be useful as a power amplifying device for digital hand-held phone because the high linear gain can deliver a high power added efficiency in the linear operation region of output power and the high third-order intercept point can reduce the third-order inter modulation.

• The Journal of Korean Institute of Next Generation Computing
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• 제15권2호
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• pp.7-16
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• 2019

Neural networks can be implemented in variety of ways, and specialized chips is being developed for hardware improvement. In order to apply such neural networks to wearable devices, the compactness and the low power operation are essential. In this point of view, a suitable implementation method is a digital circuit design using field programmable gate array (FPGA). To implement this system, the learning algorithm which takes up a large part in neural networks must be implemented within FPGA for better performance. In this paper, a back propagation algorithm among various learning algorithms is implemented using FPGA, and this neural network is verified by OR gate operation. In addition, it is confirmed that this neural network can be used to analyze various users' bio signal measurement results by learning algorithm.

• Journal of Sensor Science and Technology
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• 제6권3호
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• pp.221-227
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• 1997

The Pd/NiCr gate MISFET-type sensors were fabricated for detecting hydrogen dissolved in high-capacivity transformer oil. To improve stability and high concentration sensitivity of the sensor, Pd/NiCr double catalysis metal gate was used. To reduce the serious gate voltage drift of the sensor induced by hydrogen, the gate insulators of 2 FETs were constructed with double layer of silicon dioxide and silicon nitride. The hydrogen sensitivity of the Pd/NiCr gate MISFET is about a half of Pd/Pt gate MISFET's sensitivity but the Pd/NiCr gate MISFET has good stability and high concentration detectivity up to 1000 ppm.

• Proceedings of the Korean Society of Agricultural Engineers Conference
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• 한국농공학회 2005년도 학술발표논문집
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• pp.306-312
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• 2005

Gates for the purpose of drainage are classified following the types of structure as: Radial Gate, Sluice Gate, Rolling Gate, Drum Gate. In many cases of the reclamation project the sluice type of gates are applied. Different from this general trend, however the radial type of gate was adopted in the Saemangeum project. In this case the discharge coefficients which are used for the sluice type of gate was applied. To estimate the correct amount of discharge which will be evacuated through the gates, therefore the proper discharge coefficients should be estimated before the operation of the gates. The discharge coefficients were estimated through the physical hydraulic modeling, and we got the results as: $0.72{\sim}0.84$ for the submerged condition on the both sides of upstream and downstream, $0.62{\sim}0.83$ for the free surface condition on the downtream side only, and $1.04{\sim}1.12$ for the free surface condition on the both sides of upstream and downstream. The discharge coefficients obtained from the experiments are greater than those of the sluice gates in the design criteria. From the results of the study we may expect that in the Saemangeum project the radial gates could evacuate larger amount of discharge than the originally designed discharge, so that we may sure that the Saemangeum gates have enough capability to control the evacuation of water not only in the usual period but also in the flooding season.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제7권2호
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• pp.263-268
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• 2003

In this paper, we have investigated double gate (DG) MOSFET structure, which has main gate (NG) and two side gates (SG). We know that optimum side gate voltage for each side gate length is about 3V in the main gate 50nm. Also, we know that optimum side gate length for each for main gate length is about 70nm. DG MOSFET shows a small threshold voltage roll-off. From the I-V characteristics, we obtained IDsat=550$mutextrm{A}$/${\mu}{\textrm}{m}$ at VMG=VDS=1.5V and VSG=3.0V for DG MOSFET with the main gate length of 50nm and the side gate length of 70nm. The subthreshold slope is 86.2㎷/decade, transconductance is 114$mutextrm{A}$/${\mu}{\textrm}{m}$ and DIBL (Drain Induced Barrier Lowering) is 43.37㎷. Then, we have investigated the advantage of this structure for the application to multi-input NAND gate logic. Then, we have obtained very high cut-off frequency of 41.4GHz in the DG MOSFET.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권3호
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• pp.157-163
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• 2002

A new flash EEPROM device with p^＋ poly-Si control gate and n^＋ poly-Si floating side gate was fabricated and characterized. The n^＋ poly-Si gate is formed on both sides of the p^＋ poly-Si gate, and controls the underneath channel conductivity depending on the number of electron in it. The cell was programmed by hot-carrier-injection at the drain extension, and erased by direct tunneling. The proposed EEPROM cell can be scaled down to 50 nm or less. Shown were measured programming and erasing characteristics. The channel resistance with the write operation was increased by at least 3 times.

• Journal of Electrical Engineering and Technology
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• 제9권2호
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• pp.649-654
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• 2014

In this paper, an analytical model for Surrounding Gate (SG) metal-oxide- semiconductor field effect transistors (MOSFETs) considering quantum effects is presented. To achieve this goal, we have used variational approach for solving the Poission and Schrodinger equations. This model is developed to provide an analytical expression for inversion charge distribution function for all regions of device operation. This expression is used to calculate the other important parameters like inversion charge density, threshold voltage, drain current and gate capacitance. The calculated expressions for the above parameters are simple and accurate. This paper also focuses on the gate tunneling issue associated with high dielectric constant. The validity of this model was checked for the devices with different dimensions and bias voltages. The calculated results are compared with the simulation results and they show good agreement.

• Journal of IKEEE
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• 제25권4호
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• pp.774-777
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• 2021

In this paper, we analyzed the gate controllability of 3D NAND Flash Memory with Charge Trap Flash using Ferroelectric (CTF-F) structure. HfO₂, a ferroelectric material, has a high-k characteristic besides polarization. Due to these characteristics, gate controllability is increased in CTF-F structure and on/off current characteristics are improved in Bit Line(BL). As a result of the simulation, in the CTF-F structure, the channel length of String Select Line(SSL) and Ground Select Line(GSL) was 100 nm, which was reduced by 33% compared to the conventional CTF structure, but almost the same off-current characteristics were confirmed. In addition, it was confirmed that the inversion layer was formed stronger in the channel during the program operation, and the current through the BL was increased by about 2 times.

• The Sea:JOURNAL OF THE KOREAN SOCIETY OF OCEANOGRAPHY
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• 제11권4호
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• pp.133-144
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• 2006

It is investigated using ADCIRC model to find an optimal gate operation in order to maintain target water level of the inner Saemangeum Reservoir. Various developing procedures and river inflows conditions are considered in modeling. For the gate operations, consecutive openings to inflow and outflow, such as once a day, twice a day and once per two days are considered. However water level increases gradually due to river inflows regardless of gate operations. In order to maintain target level 0.0 m, it is recommended to shut down of gate in order to prevent inflows of outer sea water at least once per 6 days for normal riverine inflows and once per 3 days for flood inflows during consecutive operations. Then it is balanced within maximum of ${\pm}0.4m$ of deviations from target level of 0.0 meter.

• Journal of information and communication convergence engineering
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• 제9권4호
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• pp.435-440
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• 2011

This paper propose the method of constructing the highly efficiency adder and multiplier systems over finite fields. The addition arithmetic operation over finite field is simple comparatively because that addition arithmetic operation is analyzed by each digit modP summation independently. But in case of multiplication arithmetic operation, we generate maximum k=2m-2 degree of ${\alpha}^k$ terms, therefore we decrease k into m-1 degree using irreducible primitive polynomial. We propose two method of control signal generation for the purpose of performing above decrease process. One method is the combinational logic expression and the other method is universal signal generation. The proposed method of constructing the highly adder/multiplier systems is as following. First of all, we obtain algorithms for addition and multiplication arithmetic operation based on the mathematical properties over finite fields, next we construct basic cell of A-cell and M-cell using T-gate and modP cyclic gate. Finally we construct adder module and multiplier module over finite fields after synthesizing ${\alpha}^k$ generation module and control signal CSt generation module with A-cell and M-cell. Next, we constructing the arithmetic operation unit over finite fields. Then, we propose the future research and prospects.