Journal of information and communication convergence engineering

  • 제9권4호
  • /
  • Pages.435-440
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  • 2011
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  • 2234-8255(pISSN)
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  • 2234-8883(eISSN)
한국정보통신학회 (The Korea Institute of Information and Commucation Engineering)
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An Arithmetic System over Finite Fields

  • Park, Chun-Myoung (Department of Computer Engineering, Chungju National University)
  • 투고 : 2011.07.22
  • 심사 : 2011.08.10
  • 발행 : 2011.08.31
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초록

This paper propose the method of constructing the highly efficiency adder and multiplier systems over finite fields. The addition arithmetic operation over finite field is simple comparatively because that addition arithmetic operation is analyzed by each digit modP summation independently. But in case of multiplication arithmetic operation, we generate maximum k=2m-2 degree of ${\alpha}^k$ terms, therefore we decrease k into m-1 degree using irreducible primitive polynomial. We propose two method of control signal generation for the purpose of performing above decrease process. One method is the combinational logic expression and the other method is universal signal generation. The proposed method of constructing the highly adder/multiplier systems is as following. First of all, we obtain algorithms for addition and multiplication arithmetic operation based on the mathematical properties over finite fields, next we construct basic cell of A-cell and M-cell using T-gate and modP cyclic gate. Finally we construct adder module and multiplier module over finite fields after synthesizing ${\alpha}^k$ generation module and control signal CSt generation module with A-cell and M-cell. Next, we constructing the arithmetic operation unit over finite fields. Then, we propose the future research and prospects.

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참고문헌

  1. D. Green, Modern Logic Design, Addison-Wesley company, 1986.
  2. K. Hwang, Computer Arithmetic principles, architecture, and design, john Wiley & Sons, 1979.
  3. H. Wu, M.A. Hasan, I.F. Blake and S. Geo, "Finite Field Multiplier Using Redundant Representation", IEEE Trans. Comput., vol.51, no.11, pp. 1306-13 16, December 2002. https://doi.org/10.1109/TC.2002.1047755
  4. W. Geiselmann and R. Steinwandt, "A Redundant Representation of GF($q^{n}$) for designing Arithmetic Circuit", IEEE Trans. Comput., vol.52, no.7, pp.848-853, July 2003. https://doi.org/10.1109/TC.2003.1214334
  5. A. Reyhani-Masoleh and M.A. Hsan, "Fast Normal basis Multiplication Using general Purpose Processors," IEEE Trans. Comput., vol.52, no. 11, pp.1379-1390, November 2003. https://doi.org/10.1109/TC.2003.1244936
  6. M.E. Kaihara and N. Takagi, "A Hardware Algorithm for Modular Multiplication/Division", IEEE Trans. Comput., vol.54, no.1, pp.12-21, January 2005. https://doi.org/10.1109/TC.2005.1
  7. C. Efstathiou, H.T. Vergos and D. Nikolas. "Modified Modulo $2^{n}$-1 Multipliers", IEEE Trans. Comput., vol.53, no.3, pp.370-374, March 2004. https://doi.org/10.1109/TC.2004.1261842
  8. C.H. Wu, C.M. Wu, M.D. shieh and Y.T. Hwang, "High-Speed, Low-Complexity systolic Design of Novel Iterative Division Algorithms in GF($2^{m}$)", IEEE Trans. Comput., vol.53, no.3, pp.375-379, March 2004. https://doi.org/10.1109/TC.2004.1261843
  9. E. Artin, Galois Theory, NAPCO Graphics arts, Inc., Wisconsin. 1971.
  10. R. Lidi and H. Niederreiter, Introduction to finite fields and their applications, Cambridge University Press, 1986.
  11. C.C. Wang," an algorithm to design finite field multipliers using a self-dual normal basis", IEEE Trans. Comput., vol.3, no.10, pp.1457-1460, Oct. 1989.
  12. C. Ling and J. Lung," Systolic array implementation of multipliers for finite fields GF($2^{m}$)", IEEE Trans. Cir. & Sys., vol.38, no.7, pp.796-800, Jul. 1991. https://doi.org/10.1109/31.135751
  13. S.T.J.Fenn, M.Benaissa and D.Taylor," GF($2^{m}$) multiplication and Division over dual basis", IEEE Trans. Comput., vol.45, no.3, pp.319-327, Mar. 1996. https://doi.org/10.1109/12.485570