• 한국항해학회지
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• 제21권2호
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• pp.69-75
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• 1997

A modern electric system located at a certain distance from the discharge may respond with unexpected sensitivity, when an electrostatic discharge (ESD) phenomenon occurs heteronomously between metallic objects. For analyzing the transient electromagnetic fields caused by ESD, two resistance formulas - Toepler and Rompe-Weizel -are introduced. The experimental result given by Wilson-Ma are used to compare which of these resistance formulas is proper.

• 전자공학회논문지A
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• 제30A권12호
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• pp.88-97
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• 1993

Electrostatic Discharge(ESD) is one of the major reliability, issues for today's VLSI production. Since the gate oxide with a thickness of 100~300$\AA$ is vulnerable to several thousand volt of ESD surge, it is necessary to control the ESD events and design an efficient protection circuit. In this paper, physical mechanism of the catastrophic ESD damage is investigated by transient analysis based upon Human Body Model(HBM). Using two-dimensional electrothermal simulator, we study the failure mechanism of the output protection devices by ESD and discuss the design issues for the optimun protection network.

• 한국소음진동공학회논문집
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• 제16권1호
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• pp.75-80
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• 2006

This paper introduces the mechanism of the ESD(electrostatic discharge) in the HDD spindle system using FDBs(fluid dynamic bearings). When a HDD(hard disk drive) spindle system is rotating, triboelectric charging occurs in the FDBs through the friction between the lubricant and the rotating shaft or between the lubricant and stationary sleeve. And this electrostatic charge is accumulated in the rotating parts of the HDD spindle system because they are insulated from the ground by the lubricant. This research shows experimentally that the behavior of electric charge and discharge in the FDB spindle system is the same as that of a capacitor. It also measures the electrostatic voltage difference between the rotating and stationary parts in the FDB spindle system due to the change of humidity, supporting load and motor speed. This research shows that the control of ESD is required in the HDD spindle system using FDBs, because the electrostatic charge accumulated in the FDB spindle system may cause the breakdown damage of the GMR head and data loss consequently.

• 대한전자공학회논문지SD
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• 제45권3호
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• pp.6-21
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• 2008

Electrostatic Discharge (ESD) 펄스의 누적이 산화형 표면 발광 반도체 레이저 (oxide VCSEL)의 전기 및 광학적 특성의 열화에 미치는 영향에 대하여 살펴보았다. 순방향 ESD의 누적에 따른 열화 과정은 3 단계의 열화과정을 보이는 반면 역방향 ESD의 인가에 따른 열화 과정은 급격한 전기 및 광학적 특성 변화에 의하여 구분되는 2 단계의 열화과정을 보였다. 등가회로 모델 및 대신호 등가회로 모델을 이용하여 I-V 특성 및 그 미분특성을 분석함으로써 두 가지 ESD 조건에 의한 산화형 VCSEL의 전기 및 광학적 특성의 열화과정을 이해할 수 있었다.

• 한국위성정보통신학회논문지
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• 제8권4호
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• pp.124-129
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• 2013

PPS 구조가 삽입된 N형 실리콘 제어 정류기 소자를 마이크로 칩의 고전압 I/O 응용을 위해 연구하였다. 종래의 NSCR_PPS_Std 표준소자는 매우 낮은 스냅백 홀딩 전압을 갖는 전형적인 SCR 특성을 가지고 있어 정상적인 동작 동안 래치업 문제가 나타나는 것으로 보고되고 있다. 그러나 본 연구에서 제안하는 CPS 및 부분적으로 형성된 P-Well(PPW) 구조를 갖는 변형된 NSCR_PPS_CPS_PPW 소자는 높은 래치업 면역과 트리거링 전압의 조절이 용이한 안정한 ESD 보호 성능을 나타내어 고전압 동작용 마이크로 칩의 정전기보호 소자로 적용 가능함을 확인하였다.

• ETRI Journal
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• 제39권5호
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• pp.746-755
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• 2017

In this paper, an electrostatic discharge (ESD) protection circuit is designed for use as a 12 V power clamp by using a parasitic-diode-triggered silicon controlled rectifier. The breakdown voltage and trigger voltage ($V_t$) of the proposed ESD protection circuit are improved by varying the length between the n-well and the p-well, and by adding $n^+/p^+$ floating regions. Moreover, the holding voltage ($V_h$) is improved by using segmented technology. The proposed circuit was fabricated using a $0.18-{\mu}m$ bipolar-CMOS-DMOS process with a width of $100{\mu}m$. The electrical characteristics and robustness of the proposed ESD circuit were analyzed using transmission line pulse measurements and an ESD pulse generator. The electrical characteristics of the proposed circuit were also analyzed at high temperature (300 K to 500 K) to verify thermal performance. After optimization, the $V_t$ of the proposed circuit increased from 14 V to 27.8 V, and $V_h$ increased from 5.3 V to 13.6 V. The proposed circuit exhibited good robustness characteristics, enduring human-body-model surges at 7.4 kV and machine-model surges at 450 V.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권3호
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• pp.339-344
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• 2014

This paper presents a novel bipolar junction transistor (BJT) based electrostatic discharge (ESD) protection device. This protection device was designed for 20V power clamps and fabricated by a process with Bipolar-CMOS-DMOS (BCD) $0.18{\mu}m$. The current-voltage characteristics of this protection device was verified by the transmission line pulse (TLP) system and the DC BV characteristic was verified by using a semiconductor parameter analyzer. From the experimental results, the proposed device has a trigger voltage of 29.1V, holding voltage of 22.4V and low on-resistance of approximately $1.6{\Omega}$. In addition, the test of ESD robustness showed that the ESD successfully passed through human body model (HBM) 8kV. In this paper, the operational mechanism of this protection device was investigated by structural analysis of the proposed device. In addition, the proposed device were obtained as stack structures and verified.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.3-4
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• 2009

As device process technology advances, effective channel length, the thickness of gate oxide, and supply voltage decreases. This paper describes a novel electrostatic discharge (ESD) protection device which has current feedback for high ESD immunity. A conventional Gate-Grounded NMOS (GGNMOS) transistor has only one ESD current path, which makes, the core circuit be in the safe region, so an GGNMOS transistor has low current immunity compared with our device which has current feedback path. To simulate our device, we use conventional $0.18\;{\mu}m$ technology parameters with a gate oxide thickness of $43\;{\AA}$ and power supply voltage of 1.8 V. Our simulation results indicate that the area of our ESD protection, device can be smaller than a GGNMOS transistor, and ESD immunity is better than a GGNMOS transistor.

• 한국전기전자재료학회논문지
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• 제27권11호
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• pp.686-689
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• 2014

Electrostatic discharge has been considered as a major reliability problem in the semiconductor industry. ESD reliability is an important issue for these products. Therefore, each I/O (Input/Output) PAD must be designed with a protection circuitry that creates a low impedance discharge path for ESD current. This paper presents a novel Lateral Insulated Gate Bipolar (LIGBT)-based ESD protection circuit with latch-up immunity and high robustness. The proposed circuit is fabricated by using 0.18 um BCD (bipolar-CMOS-DMOS) process. Also, TLP (transmission line pulse) I-V characteristic of proposed circuit is measured. In the result, the proposed ESD protection circuit has latch-up immunity and high robustness. These characteristics permit the proposed circuit to apply to power clamp circuit. Consequently, the proposed LIGBT-based ESD protection circuit with a latch-up immune characteristic can be applied to analog integrated circuits.

• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2006년도 하계학술대회
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• pp.208-211
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• 2006

In this paper, a tunable image rejection filter using two varactors is developed for mobile convergence. The filter is fabricated on a 0.25um substrate. ESD Pad is embedded to prevent damage caused by electrostatic discharge(ESD). Bias voltages are at WCDMA(2.1GHz). WiBro(2.3GHz), and WLAN(2.45) are 0.5V, 0.95V and 1.8V respectively. And the image rejection rations are more than 28dB at each band and insertion losses are less than 2dB at each band.