• Title/Summary/Keyword: Drain current

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Gate-Induced-Drain-Leakage (GIDL) Current of MOSFETs with Channel Doping and Width Dependence

  • Choi, Byoung-Seon;Choi, Pyung-Ho;Choi, Byoung-Deog
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.344-345
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    • 2012
  • The Gate-Induced-Drain-Leakage (GIDL) current with channel doping and width dependence are characterized. The GIDL currents are found to increase in MOSFETs with higher channel doping levels and the observed GIDL current is generated by the band-to-band-tunneling (BTBT) of electron through the reverse-biased channel-to-drain p-n junction. A BTBT model is used to fit the measured GIDL currents under different channel-doping levels. Good agreement is obtained between the modeled results and experimental data. The increase of the GIDL current at narrower widths in mainly caused by the stronger gate field at the edge of the shallow trench isolation (STI). As channel width decreases, a larger portion of the GIDL current is generated at the channel-isolation edge. Therefore, the stronger gate field at the channel-isolation edge causes the total unit-width GIDL current to increases for narrow-width devices.

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Analysis of a Novel Elevated Source Drain MOSFET with Reduced Gate-Induced Drain Leakage and High Driving Capability (Gate-Induced Drain Leakage를 줄인 새로운 구조의 고성능 Elevated Source Drain MOSFET에 관한 분석)

  • Kim, Gyeong-Hwan;Choe, Chang-Sun;Kim, Jeong-Tae;Choe, U-Yeong
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.6
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    • pp.390-397
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    • 2001
  • A novel self-aligned ESD (Elevated Source Drain) MOSFET structure which can effectively reduce the GIDL (Gate-Induced Drain Leakage) current is proposed and analyzed. The proposed ESD structure is characterized by sidewall spacer and recessed-channel depth which are determined by dry-etching process. Elevation of the Source/Drain extension region is realized so that the low-activation effect caused by low-energy ion implantation can be avoided. Unlike the conventional LDD structures, it is shown that the GIDL current of the ESD structure is suppressed without sacrificing the maximum driving capability. The main reason for the reduction of GIDL current Is the decreased electric field at the point of the maximum band-to-band tunneling as the peak electric field is shifted toward the drain side.

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Current Modeling for Accumulation Mode GaN Schottky Barrier MOSFET for Integrated UV Sensors

  • Park, Won-June;Hahm, Sung-Ho
    • Journal of Sensor Science and Technology
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    • v.26 no.2
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    • pp.79-84
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    • 2017
  • The drain current of the SB MOSFET was analytically modeled by an equation composed of thermionic emission and tunneling with consideration of the image force lowering. The depletion region electron concentration was used to model the channel electron concentration for the tunneling current. The Schottky barrier width is dependent on the channel electron concentration. The drain current is changed by the gate oxide thickness and Schottky barrier height, but it is hardly changed by the doping concentration. For a GaN SB MOSFET with ITO source and drain electrodes, the calculated threshold voltage was 3.5 V which was similar to the measured value of 3.75 V and the calculated drain current was 1.2 times higher than the measured.

The Characteristics of Degraded Drain Output Resistance of NMOSFET due to Hot Electron Effects (Hot electron 효과로 노쇠화된 NMOSFET의 드레인 출력저항 특성)

  • 김미란;박종태
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.30A no.9
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    • pp.38-45
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    • 1993
  • In this study, the degradation characteristics of drain output resis-tance was described due to hot electron effects. An semi-empirical model for the degraded drain output resistance was derived from the measured device characteristics. The suggested model was verified from the measured data and the device parameter dependence was also analyzed. The degradation of drain output resistance was increased with stress time and had linear relationship with the degradation of drain current. The device lifetime which was defined by failure criteria of drain output resistance (such as $\Delta$ro/roo=5%) was equivalent to that of failure criteria of drain current (such as $\Delta$ID/ID=5%)

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Electrical Characteristics and Models for Asymmetric n-MOSFET′s with Irregular Source/Drain Contacts (불규칙한 소오스/드레인 금속 접촉을 갖는 비대칭 n-MOSFET의 전기적 특성 및 모델)

  • 공동욱;정환희;이재성;이용현
    • Proceedings of the IEEK Conference
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    • 1999.11a
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    • pp.208-211
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    • 1999
  • Abstract - Electrical characteristics or asymmetric n-MOSFET's with different source and drain geometry are experimently investigated using test structures having various gate width. Saturation drain current and resistance in linear region are estimated by a simple schematic model, which consists of conventional device having parasitic resistor. A comparison of experimental results of symmetric and asymmetric devices gives the parasitic resistance caused by abnormal device structure. The suggested model shows good agreement with the measured drain current for both forward- and reverse-modes.

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28 nm MOSFET Design for Low Standby Power Applications (저전력 응용을 위한 28 nm 금속 게이트/high-k MOSFET 디자인)

  • Lim, To-Woo;Jang, Jun-Yong;Kim, Young-Min
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.57 no.2
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    • pp.235-238
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    • 2008
  • This paper explores 28 nm MOSFET design for LSTP(Low Standby Power) applications using TCAD(Technology Computer Aided Design) simulation. Simulated results show that the leakage current of the MOSFET is increasingly dominated by GIDL(Gate Induced Drain Leakage) instead of a subthreshold leakage as the Source/Drain extension doping increases. The GIDL current can be reduced by grading lateral abruptness of the drain at the expense of a higher Source/Drain series resistance. For 28 nm MOSFET suggested in ITRS, we have shown Source/Drain design becomes even more critical to meet both leakage current and performance requirement.

Simulation of nonoverlapped source/drain-to-gate Nano-CMOS for low leakage current (낮은 누설전류를 위한 소스/드레인-게이트 비중첩 Nano-CMOS구조 전산모사)

  • Song, Seung-Hyun;Lee, Kang-Sung;Jeong, Yoon-Ha
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.579-580
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    • 2006
  • Simple nonoverlapped source/drain-to-gate MOSFETs to suppress GIDL (gate-induced drain leakage) is simulated with SILVACO simulation tool. Changing spacer thickness for adjusting length of Drain to Gate nonoverlapped region, this simulation observes on/off characteristic of nonoverlapped source/drain-to-gate MOSFETs. Off current is dramatically decreased with S/D to gate nonoverlapped length increasing. The result shows that maximum on/off current ratio is achieved by adjusting nonoverlapped length.

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Reduction of Drain Leakage Current by AlGaAs buffer layer in GaAs MESFET (GaAs MESFET에서 AlGaAs buffer layer에 의한 Drain 누설전류 차단)

  • Park, Jun;Jo, Jung-Yol
    • Proceedings of the KIEE Conference
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    • 1998.07d
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    • pp.1321-1323
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    • 1998
  • We investigated drain leakage current in GaAs power MESFET. The device we studied by 20 simulation has a $1000{\AA}$ thick AlGaAs buffer layer under n-GaAs active layer. The calculation shows that the leakage current through GaAs substrate is significantly reduced by the buffer layer.

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The Fabrication and Characterization of CODE MOSFET (CODE MOSFET 소자의 제작 및 특성)

  • 송재혁;김기홍;박영준;민홍식
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.27 no.6
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    • pp.895-900
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    • 1990
  • With the MOS device scailing down, the substrate concentration must increase in order to avoid punchthrough leakage current due to the DIBL(Drain Induced Barrier Lowering) effect. However the enhancement of the substrate concentration increases source, drain juntion capacitances and substrate current due to hot elelctron, degrading the speed characteristics and reliability of the MOS devices. In this paper, a new device, called CODE(Channel Only Dopant Enhancement) MOS, an its fabrication are proposed. By comparing the fabricated CODE MOSFET with the conventional device, the improvements on DIBL, substrate current and source, drain juntion capacitances are realized.

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Output Characteristics of Carbon-nanotube Field-effect Transistor Dependent on Nanotube Diameter and Oxide Thickness (나노튜브 직경과 산화막 두께에 따른 탄소나노튜브 전계 효과 트랜지스터의 출력 특성)

  • Park, Jong-Myeon;Hong, Shin-Nam
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.26 no.2
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    • pp.87-91
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    • 2013
  • Carbon-nanotube field-effect transistors (CNFETs) have drawn wide attention as one of the potential substitutes for metal-oxide-semiconductor field-effect transistors (MOSFETs) in the sub-10-nm era. Output characteristics of coaxially gated CNFETs were simulated using FETToy simulator to reveal the dependence of drain current on the nanotube diameter and gate oxide thickness. Nanotube diameter and gate oxide thickness employed in the simulation were 1.5, 3, and 6 nm. Simulation results show that drain current becomes large as the diameter of nanotube increases or insulator thickness decreases, and nanotube diameter affects the drain current more than the insulator thickness. An equation relating drain saturation current with nanotube diameter and insulator thickness is also proposed.