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28 nm MOSFET Design for Low Standby Power Applications  

Lim, To-Woo (홍익대 대학원 전기정보제어공학과)
Jang, Jun-Yong (홍익대 대학원 전기정보제어공학과)
Kim, Young-Min (홍익대 공대 전자전기공학부)
Publication Information
The Transactions of The Korean Institute of Electrical Engineers / v.57, no.2, 2008 , pp. 235-238 More about this Journal
Abstract
This paper explores 28 nm MOSFET design for LSTP(Low Standby Power) applications using TCAD(Technology Computer Aided Design) simulation. Simulated results show that the leakage current of the MOSFET is increasingly dominated by GIDL(Gate Induced Drain Leakage) instead of a subthreshold leakage as the Source/Drain extension doping increases. The GIDL current can be reduced by grading lateral abruptness of the drain at the expense of a higher Source/Drain series resistance. For 28 nm MOSFET suggested in ITRS, we have shown Source/Drain design becomes even more critical to meet both leakage current and performance requirement.
Keywords
GIDL; Lateral abruptness; Series resistance;
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  • Reference
1 J.D. Bude, " MOSFET Modeling Into the Ballistic Regime," SISPAD 2000, pp. 23-26
2 Semiconductor Industry Association, "The International Technology Roadmap for Semiconductors 2006 Update."
3 J.W. Sleight, I. Lauer, O. Dokumaci, D. M. Fried, D. Guo, B. Haran, S. Narasimha, C. Sheraw, D. Singh, M. Steigerwalt, X. Wang, P. Oldiges, D. Sadana, C.Y. Sung, W. Haensch, and M. Khare, "Challenges and Opportunities for High Performance 32 nm CMOS Technology," in IEDM Tech. Dig., 2006, pp. 697-700
4 Mohan V. Dunga, Chung-Hsun Lin, Darsen D. Lu1,Weize Xiong, C. R. Cleavelin, P. Patruno, Jiunn-Ren Hwang, Fu-Liang Yang, Ali M. Niknejad and Chenming Hu, "BSIM-MG: A Versatile Multi-Gate FET Model for Mixed-Signal Design,"in VLSI Symp. Tech. Dig., 2007, pp, 60-61
5 M.J.H.van Dal, N. Collaert, G. Doornbos, G. Vellianitis, G. Curatola, B.J. Pawlak, R. Duffy, C. Jonville, B. Degroote, E. Altamirano, E. Kunnen, M. Demand, S. Beckx, T. Vandeweyer, C. Delvaux, F. Leys, A. Hikavyy, R. Rooyackers, M. Kaiser, R.G.R. Weemaes, S. Biesemans, M. Jurczak, K. Anil, L. Witters and R.J.P. Lander, "Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography," in VLSI Symp. Tech. Dig., 2007, pp. 110-111
6 G. A. M. Hurkx, D. B. M. Klaassen, and M. P. G. Knuvers, "A New Recombination Model for Device Simulation Including Tunneling," IEEE Trans. Electron Devices, vol. 39, no. 2, pp. 331-338, Feb. 1992   DOI   ScienceOn