Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Simulation of nonoverlapped source/drain-to-gate Nano-CMOS for low leakage current

낮은 누설전류를 위한 소스/드레인-게이트 비중첩 Nano-CMOS구조 전산모사

  • Song, Seung-Hyun (Department of Electronic and Electrical Engineering Pohang University of Science and Technology) ;
  • Lee, Kang-Sung (Department of Electronic and Electrical Engineering Pohang University of Science and Technology) ;
  • Jeong, Yoon-Ha (Department of Electronic and Electrical Engineering Pohang University of Science and Technology)
  • 송승현 (포항공과대학교 전자전기공학과) ;
  • 이강승 (포항공과대학교 전자전기공학과) ;
  • 정윤하 (포항공과대학교 전자전기공학과)
  • Published : 2006.06.21
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Abstract

Simple nonoverlapped source/drain-to-gate MOSFETs to suppress GIDL (gate-induced drain leakage) is simulated with SILVACO simulation tool. Changing spacer thickness for adjusting length of Drain to Gate nonoverlapped region, this simulation observes on/off characteristic of nonoverlapped source/drain-to-gate MOSFETs. Off current is dramatically decreased with S/D to gate nonoverlapped length increasing. The result shows that maximum on/off current ratio is achieved by adjusting nonoverlapped length.

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